drm/amdgpu: Fix a typo

[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / amdgpu / psp_v11_0.c

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index bd4248c..5ade76a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -392,37 +392,6 @@ static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
        return ret;
 }
 
-static void psp_v11_0_reroute_ih(struct psp_context *psp)
-{
-       struct amdgpu_device *adev = psp->adev;
-       uint32_t tmp;
-
-       /* Change IH ring for VMC */
-       tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
-       tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
-       tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
-
-       WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
-       WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
-       WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
-
-       mdelay(20);
-       psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
-                    0x80000000, 0x8000FFFF, false);
-
-       /* Change IH ring for UMC */
-       tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
-       tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
-
-       WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
-       WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
-       WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
-
-       mdelay(20);
-       psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
-                    0x80000000, 0x8000FFFF, false);
-}
-
 static int psp_v11_0_ring_init(struct psp_context *psp,
                              enum psp_ring_type ring_type)
 {
@@ -430,11 +399,6 @@ static int psp_v11_0_ring_init(struct psp_context *psp,
        struct psp_ring *ring;
        struct amdgpu_device *adev = psp->adev;
 
-       if ((!amdgpu_sriov_vf(adev)) &&
-           !(adev->asic_type >= CHIP_SIENNA_CICHLID &&
-           adev->asic_type <= CHIP_DIMGREY_CAVEFISH))
-               psp_v11_0_reroute_ih(psp);
-
        ring = &psp->km_ring;
 
        ring->ring_type = ring_type;
@@ -697,9 +661,9 @@ static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops)
 
        if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
                /*
-                * Long traing will encroach certain mount of bottom VRAM,
-                * saving the content of this bottom VRAM to system memory
-                * before training, and restoring it after training to avoid
+                * Long training will encroach a certain amount on the bottom of VRAM;
+                * save the content from the bottom of VRAM to system memory
+                * before training, and restore it after training to avoid
                 * VRAM corruption.
                 */
                sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE;
@@ -726,7 +690,7 @@ static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops)
                }
 
                memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
-               adev->nbio.funcs->hdp_flush(adev, NULL);
+               adev->hdp.funcs->flush_hdp(adev, NULL);
                vfree(buf);
        }