drm/amdgpu: add rlc iram and dram firmware support

[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / amdgpu / psp_gfx_if.h

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
index cbc04a5..4137dc7 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
+++ b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
@@ -83,19 +83,6 @@ struct psp_gfx_ctrl
 */
 #define GFX_FLAG_RESPONSE               0x80000000
 
-/* Gbr IH registers ID */
-enum ih_reg_id {
-       IH_RB           = 0,            // IH_RB_CNTL
-       IH_RB_RNG1      = 1,            // IH_RB_CNTL_RING1
-       IH_RB_RNG2      = 2,            // IH_RB_CNTL_RING2
-};
-
-/* Command to setup Gibraltar IH register */
-struct psp_gfx_cmd_gbr_ih_reg {
-       uint32_t                reg_value;      /* Value to be set to the IH_RB_CNTL... register*/
-       enum ih_reg_id          reg_id;         /* ID of the register */
-};
-
 /* TEE Gfx Command IDs for the ring buffer interface. */
 enum psp_gfx_cmd_id
 {
@@ -214,7 +201,7 @@ enum psp_gfx_fw_type {
        GFX_FW_TYPE_UVD1        = 23,   /* UVD1                     VG-20   */
        GFX_FW_TYPE_TOC         = 24,   /* TOC                      NV-10   */
        GFX_FW_TYPE_RLC_P                           = 25,   /* RLC P                    NV      */
-       GFX_FW_TYPE_RLX6                            = 26,   /* RLX6                     NV      */
+       GFX_FW_TYPE_RLC_IRAM                        = 26,   /* RLC_IRAM                 NV      */
        GFX_FW_TYPE_GLOBAL_TAP_DELAYS               = 27,   /* GLOBAL TAP DELAYS        NV      */
        GFX_FW_TYPE_SE0_TAP_DELAYS                  = 28,   /* SE0 TAP DELAYS           NV      */
        GFX_FW_TYPE_SE1_TAP_DELAYS                  = 29,   /* SE1 TAP DELAYS           NV      */
@@ -236,7 +223,7 @@ enum psp_gfx_fw_type {
        GFX_FW_TYPE_ACCUM_CTRL_RAM                  = 45,   /* ACCUM CTRL RAM           NV      */
        GFX_FW_TYPE_RLCP_CAM                        = 46,   /* RLCP CAM                 NV      */
        GFX_FW_TYPE_RLC_SPP_CAM_EXT                 = 47,   /* RLC SPP CAM EXT          NV      */
-       GFX_FW_TYPE_RLX6_DRAM_BOOT                  = 48,   /* RLX6 DRAM BOOT           NV      */
+       GFX_FW_TYPE_RLC_DRAM_BOOT                   = 48,   /* RLC DRAM BOOT            NV      */
        GFX_FW_TYPE_VCN0_RAM                        = 49,   /* VCN_RAM                  NV + RN */
        GFX_FW_TYPE_VCN1_RAM                        = 50,   /* VCN_RAM                  NV + RN */
        GFX_FW_TYPE_DMUB                            = 51,   /* DMUB                          RN */