drm/amdgpu: Support passing poison consumption ras block to SRIOV

[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / amdgpu / mxgpu_nv.c

diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
index 6a68ee9..d0a018d 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
@@ -152,14 +152,14 @@ static void xgpu_nv_mailbox_trans_msg (struct amdgpu_device *adev,
        xgpu_nv_mailbox_set_valid(adev, false);
 }
 
-static int xgpu_nv_send_access_requests(struct amdgpu_device *adev,
-                                       enum idh_request req)
+static int xgpu_nv_send_access_requests_with_param(struct amdgpu_device *adev,
+                       enum idh_request req, u32 data1, u32 data2, u32 data3)
 {
        int r, retry = 1;
        enum idh_event event = -1;
 
 send_request:
-       xgpu_nv_mailbox_trans_msg(adev, req, 0, 0, 0);
+       xgpu_nv_mailbox_trans_msg(adev, req, data1, data2, data3);
 
        switch (req) {
        case IDH_REQ_GPU_INIT_ACCESS:
@@ -206,6 +206,13 @@ send_request:
        return 0;
 }
 
+static int xgpu_nv_send_access_requests(struct amdgpu_device *adev,
+                                       enum idh_request req)
+{
+       return xgpu_nv_send_access_requests_with_param(adev,
+                                               req, 0, 0, 0);
+}
+
 static int xgpu_nv_request_reset(struct amdgpu_device *adev)
 {
        int ret, i = 0;
@@ -424,9 +431,15 @@ void xgpu_nv_mailbox_put_irq(struct amdgpu_device *adev)
        amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
 }
 
-static void xgpu_nv_ras_poison_handler(struct amdgpu_device *adev)
+static void xgpu_nv_ras_poison_handler(struct amdgpu_device *adev,
+               enum amdgpu_ras_block block)
 {
-       xgpu_nv_send_access_requests(adev, IDH_RAS_POISON);
+       if (amdgpu_ip_version(adev, UMC_HWIP, 0) < IP_VERSION(12, 0, 0)) {
+               xgpu_nv_send_access_requests(adev, IDH_RAS_POISON);
+       } else {
+               xgpu_nv_send_access_requests_with_param(adev,
+                                       IDH_RAS_POISON, block, 0, 0);
+       }
 }
 
 const struct amdgpu_virt_ops xgpu_nv_virt_ops = {