Merge branch 'for-4.20-fixes' into for-4.21

[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / amdgpu / gmc_v8_0.c

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 9333109..1d3265c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -27,6 +27,7 @@
 #include "gmc_v8_0.h"
 #include "amdgpu_ucode.h"
 #include "amdgpu_amdkfd.h"
+#include "amdgpu_gem.h"
 
 #include "gmc/gmc_8_1_d.h"
 #include "gmc/gmc_8_1_sh_mask.h"
@@ -410,8 +411,8 @@ static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
                base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
        base <<= 24;
 
-       amdgpu_device_vram_location(adev, &adev->gmc, base);
-       amdgpu_device_gart_location(adev, mc);
+       amdgpu_gmc_vram_location(adev, &adev->gmc, base);
+       amdgpu_gmc_gart_location(adev, mc);
 }
 
 /**
@@ -806,16 +807,20 @@ static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)
  */
 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
 {
+       uint64_t table_addr;
        int r, i;
        u32 tmp, field;
 
-       if (adev->gart.robj == NULL) {
+       if (adev->gart.bo == NULL) {
                dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
                return -EINVAL;
        }
        r = amdgpu_gart_table_vram_pin(adev);
        if (r)
                return r;
+
+       table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
+
        /* Setup TLB control */
        tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
        tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
@@ -863,7 +868,7 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
        /* setup context0 */
        WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
        WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
-       WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
+       WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
        WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
                        (u32)(adev->dummy_page_addr >> 12));
        WREG32(mmVM_CONTEXT0_CNTL2, 0);
@@ -887,10 +892,10 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
        for (i = 1; i < 16; i++) {
                if (i < 8)
                        WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
-                              adev->gart.table_addr >> 12);
+                              table_addr >> 12);
                else
                        WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
-                              adev->gart.table_addr >> 12);
+                              table_addr >> 12);
        }
 
        /* enable context1-15 */
@@ -918,7 +923,7 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
        gmc_v8_0_flush_gpu_tlb(adev, 0);
        DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
                 (unsigned)(adev->gmc.gart_size >> 20),
-                (unsigned long long)adev->gart.table_addr);
+                (unsigned long long)table_addr);
        adev->gart.ready = true;
        return 0;
 }
@@ -927,7 +932,7 @@ static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
 {
        int r;
 
-       if (adev->gart.robj) {
+       if (adev->gart.bo) {
                WARN(1, "R600 PCIE GART already initialized\n");
                return 0;
        }
@@ -1090,11 +1095,11 @@ static int gmc_v8_0_sw_init(void *handle)
                adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp);
        }
 
-       r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
+       r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
        if (r)
                return r;
 
-       r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
+       r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
        if (r)
                return r;
 
@@ -1728,8 +1733,7 @@ static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
 
 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev)
 {
-       if (adev->gmc.gmc_funcs == NULL)
-               adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs;
+       adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs;
 }
 
 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)