Merge branch 'work.fdpic' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs

[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / amdgpu / gfxhub_v1_0.c

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 6682b84..529e463 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -38,15 +38,15 @@ u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev)
 void gfxhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
                                uint64_t page_table_base)
 {
-       /* two registers distance between mmVM_CONTEXT0_* to mmVM_CONTEXT1_* */
-       int offset = mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
-                       - mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
+       struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 
        WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
-                               offset * vmid, lower_32_bits(page_table_base));
+                           hub->ctx_addr_distance * vmid,
+                           lower_32_bits(page_table_base));
 
        WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
-                               offset * vmid, upper_32_bits(page_table_base));
+                           hub->ctx_addr_distance * vmid,
+                           upper_32_bits(page_table_base));
 }
 
 static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
@@ -207,6 +207,7 @@ static void gfxhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)
 
 static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
 {
+       struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
        unsigned num_level, block_size;
        uint32_t tmp;
        int i;
@@ -245,25 +246,31 @@ static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
                tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
                                    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
                                    !amdgpu_noretry);
-               WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i, tmp);
-               WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
-               WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);
-               WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,  i*2,
-                       lower_32_bits(adev->vm_manager.max_pfn - 1));
-               WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2,
-                       upper_32_bits(adev->vm_manager.max_pfn - 1));
+               WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL,
+                                   i * hub->ctx_distance, tmp);
+               WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
+                                   i * hub->ctx_addr_distance, 0);
+               WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
+                                   i * hub->ctx_addr_distance, 0);
+               WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
+                                   i * hub->ctx_addr_distance,
+                                   lower_32_bits(adev->vm_manager.max_pfn - 1));
+               WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
+                                   i * hub->ctx_addr_distance,
+                                   upper_32_bits(adev->vm_manager.max_pfn - 1));
        }
 }
 
 static void gfxhub_v1_0_program_invalidation(struct amdgpu_device *adev)
 {
+       struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
        unsigned i;
 
        for (i = 0 ; i < 18; ++i) {
                WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
-                                   2 * i, 0xffffffff);
+                                   i * hub->eng_addr_distance, 0xffffffff);
                WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
-                                   2 * i, 0x1f);
+                                   i * hub->eng_addr_distance, 0x1f);
        }
 }
 
@@ -299,12 +306,14 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 
 void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev)
 {
+       struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
        u32 tmp;
        u32 i;
 
        /* Disable all tables */
        for (i = 0; i < 16; i++)
-               WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL, i, 0);
+               WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL,
+                                   i * hub->ctx_distance, 0);
 
        /* Setup TLB control */
        tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
@@ -360,7 +369,7 @@ void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
                                CRASH_ON_NO_RETRY_FAULT, 1);
                tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
                                CRASH_ON_RETRY_FAULT, 1);
-    }
+       }
        WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);
 }
 
@@ -386,4 +395,11 @@ void gfxhub_v1_0_init(struct amdgpu_device *adev)
                SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
        hub->vm_l2_pro_fault_cntl =
                SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
+
+       hub->ctx_distance = mmVM_CONTEXT1_CNTL - mmVM_CONTEXT0_CNTL;
+       hub->ctx_addr_distance = mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
+               mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
+       hub->eng_distance = mmVM_INVALIDATE_ENG1_REQ - mmVM_INVALIDATE_ENG0_REQ;
+       hub->eng_addr_distance = mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
+               mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
 }