Merge tag 'for-linus-5.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rw...

[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / amdgpu / gfx_v9_0.c

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 0d8e203..fc9bb94 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -794,7 +794,7 @@ static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
-                                 struct amdgpu_cu_info *cu_info);
+                               struct amdgpu_cu_info *cu_info);
 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring);
@@ -2228,7 +2228,8 @@ static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
        irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
                + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
                + ring->pipe;
-       hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue) ?
+       hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,
+                                                           ring->queue) ?
                        AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
        /* type-2 packets are deprecated on MEC, use type-3 instead */
        return amdgpu_ring_init(adev, ring, 1024,
@@ -2519,7 +2520,7 @@ static void gfx_v9_0_init_gds_vmid(struct amdgpu_device *adev)
         * the driver can enable them for graphics. VMID0 should maintain
         * access so that HWS firmware can save/restore entries.
         */
-       for (vmid = 1; vmid < 16; vmid++) {
+       for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
                WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
                WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
                WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
@@ -2992,7 +2993,7 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
        }
 }
 
-void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
+static void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
 {
        WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0);
        gfx_v9_0_enable_gui_idle_interrupt(adev, false);
@@ -3383,7 +3384,9 @@ static void gfx_v9_0_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *m
        struct amdgpu_device *adev = ring->adev;
 
        if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
-               if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) {
+               if (amdgpu_gfx_is_high_priority_compute_queue(adev,
+                                                             ring->pipe,
+                                                             ring->queue)) {
                        mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
                        mqd->cp_hqd_queue_priority =
                                AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
@@ -4633,7 +4636,8 @@ static int gfx_v9_0_early_init(void *handle)
                adev->gfx.num_gfx_rings = 0;
        else
                adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
-       adev->gfx.num_compute_rings = amdgpu_num_kcq;
+       adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
+                                         AMDGPU_MAX_COMPUTE_RINGS);
        gfx_v9_0_set_kiq_pm4_funcs(adev);
        gfx_v9_0_set_ring_funcs(adev);
        gfx_v9_0_set_irq_funcs(adev);
@@ -5177,7 +5181,7 @@ static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
 
        if (ring->use_doorbell) {
                /* XXX check if swapping is necessary on BE */
-               atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
+               atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
                WDOORBELL64(ring->doorbell_index, ring->wptr);
        } else {
                WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
@@ -5363,7 +5367,7 @@ static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
 
        /* XXX check if swapping is necessary on BE */
        if (ring->use_doorbell) {
-               atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
+               atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
                WDOORBELL64(ring->doorbell_index, ring->wptr);
        } else{
                BUG(); /* only DOORBELL method supported on gfx9 now */
@@ -5683,6 +5687,7 @@ static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
                WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
                               PRIV_INSTR_INT_ENABLE,
                               state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
+               break;
        default:
                break;
        }