Merge tag 'mips-fixes_5.14_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips...

[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / amdgpu / gfx_v9_0.c

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index c09225d..6a23c68 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -734,7 +734,7 @@ static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
        mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 };
 
-static void gfx_v9_0_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag)
+static void gfx_v9_0_rlcg_w(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag)
 {
        static void *scratch_reg0;
        static void *scratch_reg1;
@@ -787,15 +787,17 @@ static void gfx_v9_0_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32
 
 }
 
-static void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag)
+static void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset,
+                              u32 v, u32 acc_flags, u32 hwip)
 {
-       if (amdgpu_sriov_fullaccess(adev)) {
-               gfx_v9_0_rlcg_rw(adev, offset, v, flag);
+       if ((acc_flags & AMDGPU_REGS_RLC) &&
+           amdgpu_sriov_fullaccess(adev)) {
+               gfx_v9_0_rlcg_w(adev, offset, v, acc_flags);
 
                return;
        }
 
-       if (flag & AMDGPU_REGS_NO_KIQ)
+       if (acc_flags & AMDGPU_REGS_NO_KIQ)
                WREG32_NO_KIQ(offset, v);
        else
                WREG32(offset, v);
@@ -1293,6 +1295,16 @@ static bool is_raven_kicker(struct amdgpu_device *adev)
                return false;
 }
 
+static bool check_if_enlarge_doorbell_range(struct amdgpu_device *adev)
+{
+       if ((adev->asic_type == CHIP_RENOIR) &&
+           (adev->gfx.me_fw_version >= 0x000000a5) &&
+           (adev->gfx.me_feature_version >= 52))
+               return true;
+       else
+               return false;
+}
+
 static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)
 {
        if (gfx_v9_0_should_disable_gfxoff(adev->pdev))
@@ -3673,12 +3685,17 @@ static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
        if (ring->use_doorbell) {
                WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
                                        (adev->doorbell_index.kiq * 2) << 2);
-               /* If GC has entered CGPG, ringing doorbell > first page doesn't
-                * wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to workaround
-                * this issue.
+               /* If GC has entered CGPG, ringing doorbell > first page
+                * doesn't wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to
+                * workaround this issue. And this change has to align with firmware
+                * update.
                 */
-               WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
+               if (check_if_enlarge_doorbell_range(adev))
+                       WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
                                        (adev->doorbell.size - 4));
+               else
+                       WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
+                                       (adev->doorbell_index.userqueue_end * 2) << 2);
        }
 
        WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
@@ -3941,7 +3958,8 @@ static void gfx_v9_0_init_tcp_config(struct amdgpu_device *adev)
 {
        u32 tmp;
 
-       if (adev->asic_type != CHIP_ARCTURUS)
+       if (adev->asic_type != CHIP_ARCTURUS &&
+           adev->asic_type != CHIP_ALDEBARAN)
                return;
 
        tmp = RREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG);
@@ -4563,8 +4581,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
        if (!ring->sched.ready)
                return 0;
 
-       if (adev->asic_type == CHIP_ARCTURUS ||
-           adev->asic_type == CHIP_ALDEBARAN) {
+       if (adev->asic_type == CHIP_ARCTURUS) {
                vgpr_init_shader_ptr = vgpr_init_compute_shader_arcturus;
                vgpr_init_shader_size = sizeof(vgpr_init_compute_shader_arcturus);
                vgpr_init_regs_ptr = vgpr_init_regs_arcturus;
@@ -4749,7 +4766,11 @@ static int gfx_v9_0_ecc_late_init(void *handle)
        }
 
        /* requires IBs so do in late init after IB pool is initialized */
-       r = gfx_v9_0_do_edc_gpr_workarounds(adev);
+       if (adev->asic_type == CHIP_ALDEBARAN)
+               r = gfx_v9_4_2_do_edc_gpr_workarounds(adev);
+       else
+               r = gfx_v9_0_do_edc_gpr_workarounds(adev);
+
        if (r)
                return r;