drm/amdgpu: remove set but not used variable 'mc_shared_chmap'

[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / amdgpu / gfx_v8_0.c

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index ee1ccdc..14e774d 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -1710,7 +1710,7 @@ fail:
 static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
 {
        u32 gb_addr_config;
-       u32 mc_shared_chmap, mc_arb_ramcfg;
+       u32 mc_arb_ramcfg;
        u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
        u32 tmp;
        int ret;
@@ -1850,7 +1850,6 @@ static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
                break;
        }
 
-       mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
        adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
        mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
 
@@ -2103,7 +2102,7 @@ static int gfx_v8_0_sw_fini(void *handle)
                amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
 
        amdgpu_gfx_mqd_sw_fini(adev);
-       amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
+       amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
        amdgpu_gfx_kiq_fini(adev);
 
        gfx_v8_0_mec_fini(adev);
@@ -3750,6 +3749,24 @@ static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
        }
 }
 
+static void gfx_v8_0_init_gds_vmid(struct amdgpu_device *adev)
+{
+       int vmid;
+
+       /*
+        * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
+        * access. Compute VMIDs should be enabled by FW for target VMIDs,
+        * the driver can enable them for graphics. VMID0 should maintain
+        * access so that HWS firmware can save/restore entries.
+        */
+       for (vmid = 1; vmid < 16; vmid++) {
+               WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
+               WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
+               WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);
+               WREG32(amdgpu_gds_reg_offset[vmid].oa, 0);
+       }
+}
+
 static void gfx_v8_0_config_init(struct amdgpu_device *adev)
 {
        switch (adev->asic_type) {
@@ -3816,6 +3833,7 @@ static void gfx_v8_0_constants_init(struct amdgpu_device *adev)
        mutex_unlock(&adev->srbm_mutex);
 
        gfx_v8_0_init_compute_vmid(adev);
+       gfx_v8_0_init_gds_vmid(adev);
 
        mutex_lock(&adev->grbm_idx_mutex);
        /*