Merge tag 'amd-drm-next-5.14-2021-06-02' of https://gitlab.freedesktop.org/agd5f...

[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_vm_sdma.c

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
index a83a646..4229581 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
@@ -33,11 +33,11 @@
  *
  * @table: newly allocated or validated PD/PT
  */
-static int amdgpu_vm_sdma_map_table(struct amdgpu_bo *table)
+static int amdgpu_vm_sdma_map_table(struct amdgpu_bo_vm *table)
 {
        int r;
 
-       r = amdgpu_ttm_alloc_gart(&table->tbo);
+       r = amdgpu_ttm_alloc_gart(&table->bo.tbo);
        if (r)
                return r;
 
@@ -186,7 +186,7 @@ static void amdgpu_vm_sdma_set_ptes(struct amdgpu_vm_update_params *p,
  * amdgpu_vm_sdma_update - execute VM update
  *
  * @p: see amdgpu_vm_update_params definition
- * @bo: PD/PT to update
+ * @vmbo: PD/PT to update
  * @pe: byte offset of the PDE/PTE, relative to start of PDB/PTB
  * @addr: dst addr to write into pe
  * @count: number of page entries to update
@@ -197,10 +197,11 @@ static void amdgpu_vm_sdma_set_ptes(struct amdgpu_vm_update_params *p,
  * the IB.
  */
 static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p,
-                                struct amdgpu_bo *bo, uint64_t pe,
+                                struct amdgpu_bo_vm *vmbo, uint64_t pe,
                                 uint64_t addr, unsigned count, uint32_t incr,
                                 uint64_t flags)
 {
+       struct amdgpu_bo *bo = &vmbo->bo;
        enum amdgpu_ib_pool_type pool = p->immediate ? AMDGPU_IB_POOL_IMMEDIATE
                : AMDGPU_IB_POOL_DELAYED;
        unsigned int i, ndw, nptes;
@@ -238,8 +239,8 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p,
 
                if (!p->pages_addr) {
                        /* set page commands needed */
-                       if (bo->shadow)
-                               amdgpu_vm_sdma_set_ptes(p, bo->shadow, pe, addr,
+                       if (vmbo->shadow)
+                               amdgpu_vm_sdma_set_ptes(p, vmbo->shadow, pe, addr,
                                                        count, incr, flags);
                        amdgpu_vm_sdma_set_ptes(p, bo, pe, addr, count,
                                                incr, flags);
@@ -248,7 +249,7 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p,
 
                /* copy commands needed */
                ndw -= p->adev->vm_manager.vm_pte_funcs->copy_pte_num_dw *
-                       (bo->shadow ? 2 : 1);
+                       (vmbo->shadow ? 2 : 1);
 
                /* for padding */
                ndw -= 7;
@@ -263,8 +264,8 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p,
                        pte[i] |= flags;
                }
 
-               if (bo->shadow)
-                       amdgpu_vm_sdma_copy_ptes(p, bo->shadow, pe, nptes);
+               if (vmbo->shadow)
+                       amdgpu_vm_sdma_copy_ptes(p, vmbo->shadow, pe, nptes);
                amdgpu_vm_sdma_copy_ptes(p, bo, pe, nptes);
 
                pe += nptes * 8;