drm/amdgpu: add rlc iram and dram firmware support

[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ucode.c

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 183743c..1c9476a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -391,6 +391,8 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
        case CHIP_NAVI12:
        case CHIP_SIENNA_CICHLID:
        case CHIP_NAVY_FLOUNDER:
+       case CHIP_VANGOGH:
+       case CHIP_DIMGREY_CAVEFISH:
                if (!load_type)
                        return AMDGPU_FW_LOAD_DIRECT;
                else
@@ -408,7 +410,7 @@ static ssize_t show_##name(struct device *dev,                              \
                          char *buf)                                    \
 {                                                                      \
        struct drm_device *ddev = dev_get_drvdata(dev);                 \
-       struct amdgpu_device *adev = ddev->dev_private;                 \
+       struct amdgpu_device *adev = drm_to_adev(ddev);                 \
                                                                        \
        return snprintf(buf, PAGE_SIZE, "0x%08x\n", adev->field);       \
 }                                                                      \
@@ -500,6 +502,8 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
             ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL &&
             ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM &&
             ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM &&
+            ucode->ucode_id != AMDGPU_UCODE_ID_RLC_IRAM &&
+            ucode->ucode_id != AMDGPU_UCODE_ID_RLC_DRAM &&
                 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_ERAM &&
                 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_INTV &&
                 ucode->ucode_id != AMDGPU_UCODE_ID_DMCUB)) {
@@ -556,6 +560,14 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
                ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes;
                memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_srm,
                       ucode->ucode_size);
+       } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_IRAM) {
+               ucode->ucode_size = adev->gfx.rlc.rlc_iram_ucode_size_bytes;
+               memcpy(ucode->kaddr, adev->gfx.rlc.rlc_iram_ucode,
+                      ucode->ucode_size);
+       } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_DRAM) {
+               ucode->ucode_size = adev->gfx.rlc.rlc_dram_ucode_size_bytes;
+               memcpy(ucode->kaddr, adev->gfx.rlc.rlc_dram_ucode,
+                      ucode->ucode_size);
        } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MES) {
                ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
                memcpy(ucode->kaddr, (void *)((uint8_t *)adev->mes.fw->data +
@@ -628,7 +640,7 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
        struct amdgpu_firmware_info *ucode = NULL;
 
  /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo when reset/suspend */
-       if (!amdgpu_sriov_vf(adev) && (adev->in_gpu_reset || adev->in_suspend))
+       if (!amdgpu_sriov_vf(adev) && (amdgpu_in_reset(adev) || adev->in_suspend))
                return 0;
        /*
         * if SMU loaded firmware, it needn't add SMC, UVD, and VCE