drm/amdgpu: expand sdma copy_buffer interface with tmz parameter
[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ttm.c
index c10ae1c..298caa5 100644 (file)
@@ -968,7 +968,7 @@ static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
        /* Map SG to device */
        r = -ENOMEM;
        nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
-       if (nents != ttm->sg->nents)
+       if (nents == 0)
                goto release_sg;
 
        /* convert SG to linear array of pages and dma addresses */
@@ -1840,9 +1840,11 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
         *The reserved vram for memory training must be pinned to the specified
         *place on the VRAM, so reserve it early.
         */
-       r = amdgpu_ttm_training_reserve_vram_init(adev);
-       if (r)
-               return r;
+       if (!amdgpu_sriov_vf(adev)) {
+               r = amdgpu_ttm_training_reserve_vram_init(adev);
+               if (r)
+                       return r;
+       }
 
        /* allocate memory as required for VGA
         * This is used for VGA emulation and pre-OS scanout buffers to
@@ -2041,7 +2043,8 @@ static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
        num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
        num_bytes = num_pages * 8;
 
-       r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, &job);
+       r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
+                                                                       AMDGPU_IB_POOL_NORMAL, &job);
        if (r)
                return r;
 
@@ -2051,7 +2054,7 @@ static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
        dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
        dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
        amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
-                               dst_addr, num_bytes);
+                               dst_addr, num_bytes, false);
 
        amdgpu_ring_pad_ib(ring, &job->ibs[0]);
        WARN_ON(job->ibs[0].length_dw > num_dw);
@@ -2100,7 +2103,8 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
        num_loops = DIV_ROUND_UP(byte_count, max_bytes);
        num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
 
-       r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
+       r = amdgpu_job_alloc_with_ib(adev, num_dw * 4,
+                       direct_submit ? AMDGPU_IB_POOL_DIRECT : AMDGPU_IB_POOL_NORMAL, &job);
        if (r)
                return r;
 
@@ -2122,7 +2126,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
                uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
 
                amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
-                                       dst_offset, cur_size_in_bytes);
+                                       dst_offset, cur_size_in_bytes, false);
 
                src_offset += cur_size_in_bytes;
                dst_offset += cur_size_in_bytes;
@@ -2189,7 +2193,7 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
        /* for IB padding */
        num_dw += 64;
 
-       r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
+       r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_NORMAL, &job);
        if (r)
                return r;