enum amd_pm_state_type pm;
int ret;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return 0;
+ if (adev->in_gpu_reset)
+ return -EPERM;
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0)
enum amd_pm_state_type state;
int ret;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return -EINVAL;
+ if (adev->in_gpu_reset)
+ return -EPERM;
if (strncmp("battery", buf, strlen("battery")) == 0)
state = POWER_STATE_TYPE_BATTERY;
enum amd_dpm_forced_level level = 0xff;
int ret;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return 0;
+ if (adev->in_gpu_reset)
+ return -EPERM;
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0)
enum amd_dpm_forced_level current_level = 0xff;
int ret = 0;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return -EINVAL;
+ if (adev->in_gpu_reset)
+ return -EPERM;
if (strncmp("low", buf, strlen("low")) == 0) {
level = AMD_DPM_FORCED_LEVEL_LOW;
return count;
}
+ if (adev->asic_type == CHIP_RAVEN) {
+ if (!(adev->apu_flags & AMD_APU_IS_RAVEN2)) {
+ if (current_level != AMD_DPM_FORCED_LEVEL_MANUAL && level == AMD_DPM_FORCED_LEVEL_MANUAL)
+ amdgpu_gfx_off_ctrl(adev, false);
+ else if (current_level == AMD_DPM_FORCED_LEVEL_MANUAL && level != AMD_DPM_FORCED_LEVEL_MANUAL)
+ amdgpu_gfx_off_ctrl(adev, true);
+ }
+ }
+
/* profile_exit setting is valid only when current mode is in profile mode */
if (!(current_level & (AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
struct pp_states_info data;
int i, buf_len, ret;
+ if (adev->in_gpu_reset)
+ return -EPERM;
+
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0)
return ret;
enum amd_pm_state_type pm = 0;
int i = 0, ret = 0;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return 0;
+ if (adev->in_gpu_reset)
+ return -EPERM;
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0)
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return 0;
+ if (adev->in_gpu_reset)
+ return -EPERM;
if (adev->pp_force_state_enabled)
return amdgpu_get_pp_cur_state(dev, attr, buf);
unsigned long idx;
int ret;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return -EINVAL;
+ if (adev->in_gpu_reset)
+ return -EPERM;
if (strlen(buf) == 1)
adev->pp_force_state_enabled = false;
char *table = NULL;
int size, ret;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return 0;
+ if (adev->in_gpu_reset)
+ return -EPERM;
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0)
struct amdgpu_device *adev = ddev->dev_private;
int ret = 0;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return -EINVAL;
+ if (adev->in_gpu_reset)
+ return -EPERM;
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0)
* default power levels, write "r" (reset) to the file to reset them.
*
*
- * < For Vega20 >
+ * < For Vega20 and newer ASICs >
*
* Reading the file will display:
*
const char delimiter[3] = {' ', '\n', '\0'};
uint32_t type;
- if (amdgpu_sriov_vf(adev))
- return -EINVAL;
+ if (adev->in_gpu_reset)
+ return -EPERM;
if (count > 127)
return -EINVAL;
ssize_t size;
int ret;
- if (amdgpu_sriov_vf(adev))
- return 0;
+ if (adev->in_gpu_reset)
+ return -EPERM;
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0)
uint64_t featuremask;
int ret;
- if (amdgpu_sriov_vf(adev))
- return -EINVAL;
+ if (adev->in_gpu_reset)
+ return -EPERM;
ret = kstrtou64(buf, 0, &featuremask);
if (ret)
ssize_t size;
int ret;
- if (amdgpu_sriov_vf(adev))
- return 0;
+ if (adev->in_gpu_reset)
+ return -EPERM;
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0)
ssize_t size;
int ret;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return 0;
+ if (adev->in_gpu_reset)
+ return -EPERM;
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0)
int ret;
uint32_t mask = 0;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return -EINVAL;
+ if (adev->in_gpu_reset)
+ return -EPERM;
ret = amdgpu_read_mask(buf, count, &mask);
if (ret)
ssize_t size;
int ret;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return 0;
+ if (adev->in_gpu_reset)
+ return -EPERM;
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0)
uint32_t mask = 0;
int ret;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return -EINVAL;
+ if (adev->in_gpu_reset)
+ return -EPERM;
ret = amdgpu_read_mask(buf, count, &mask);
if (ret)
ssize_t size;
int ret;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return 0;
+ if (adev->in_gpu_reset)
+ return -EPERM;
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0)
int ret;
uint32_t mask = 0;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return -EINVAL;
+ if (adev->in_gpu_reset)
+ return -EPERM;
ret = amdgpu_read_mask(buf, count, &mask);
if (ret)
ssize_t size;
int ret;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return 0;
+ if (adev->in_gpu_reset)
+ return -EPERM;
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0)
int ret;
uint32_t mask = 0;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return -EINVAL;
+ if (adev->in_gpu_reset)
+ return -EPERM;
ret = amdgpu_read_mask(buf, count, &mask);
if (ret)
ssize_t size;
int ret;
- if (amdgpu_sriov_vf(adev))
- return 0;
+ if (adev->in_gpu_reset)
+ return -EPERM;
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0)
int ret;
uint32_t mask = 0;
- if (amdgpu_sriov_vf(adev))
- return -EINVAL;
+ if (adev->in_gpu_reset)
+ return -EPERM;
ret = amdgpu_read_mask(buf, count, &mask);
if (ret)
ssize_t size;
int ret;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return 0;
+ if (adev->in_gpu_reset)
+ return -EPERM;
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0)
int ret;
uint32_t mask = 0;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return -EINVAL;
+ if (adev->in_gpu_reset)
+ return -EPERM;
ret = amdgpu_read_mask(buf, count, &mask);
if (ret)
uint32_t value = 0;
int ret;
- if (amdgpu_sriov_vf(adev))
- return 0;
+ if (adev->in_gpu_reset)
+ return -EPERM;
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0)
int ret;
long int value;
- if (amdgpu_sriov_vf(adev))
- return -EINVAL;
+ if (adev->in_gpu_reset)
+ return -EPERM;
ret = kstrtol(buf, 0, &value);
uint32_t value = 0;
int ret;
- if (amdgpu_sriov_vf(adev))
- return 0;
+ if (adev->in_gpu_reset)
+ return -EPERM;
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0)
int ret;
long int value;
- if (amdgpu_sriov_vf(adev))
- return 0;
+ if (adev->in_gpu_reset)
+ return -EPERM;
ret = kstrtol(buf, 0, &value);
ssize_t size;
int ret;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return 0;
+ if (adev->in_gpu_reset)
+ return -EPERM;
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0)
long int profile_mode = 0;
const char delimiter[3] = {' ', '\n', '\0'};
+ if (adev->in_gpu_reset)
+ return -EPERM;
+
tmp[0] = *(buf);
tmp[1] = '\0';
ret = kstrtol(tmp, 0, &profile_mode);
if (ret)
return -EINVAL;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return -EINVAL;
-
if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
if (count < 2 || count > 127)
return -EINVAL;
struct amdgpu_device *adev = ddev->dev_private;
int r, value, size = sizeof(value);
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return 0;
+ if (adev->in_gpu_reset)
+ return -EPERM;
r = pm_runtime_get_sync(ddev->dev);
if (r < 0)
struct amdgpu_device *adev = ddev->dev_private;
int r, value, size = sizeof(value);
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return 0;
+ if (adev->in_gpu_reset)
+ return -EPERM;
r = pm_runtime_get_sync(ddev->dev);
if (r < 0)
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
- uint64_t count0, count1;
+ uint64_t count0 = 0, count1 = 0;
int ret;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return 0;
+ if (adev->in_gpu_reset)
+ return -EPERM;
+
+ if (adev->flags & AMD_IS_APU)
+ return -ENODATA;
+
+ if (!adev->asic_funcs->get_pcie_usage)
+ return -ENODATA;
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0)
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return 0;
+ if (adev->in_gpu_reset)
+ return -EPERM;
if (adev->unique_id)
return snprintf(buf, PAGE_SIZE, "%016llx\n", adev->unique_id);
};
static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
- uint32_t mask)
+ uint32_t mask, enum amdgpu_device_attr_states *states)
{
struct device_attribute *dev_attr = &attr->dev_attr;
const char *attr_name = dev_attr->attr.name;
enum amd_asic_type asic_type = adev->asic_type;
if (!(attr->flags & mask)) {
- attr->states = ATTR_STATE_UNSUPPORTED;
+ *states = ATTR_STATE_UNSUPPORTED;
return 0;
}
#define DEVICE_ATTR_IS(_name) (!strcmp(attr_name, #_name))
if (DEVICE_ATTR_IS(pp_dpm_socclk)) {
- if (asic_type <= CHIP_VEGA10)
- attr->states = ATTR_STATE_UNSUPPORTED;
+ if (asic_type < CHIP_VEGA10)
+ *states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
- if (asic_type <= CHIP_VEGA10 || asic_type == CHIP_ARCTURUS)
- attr->states = ATTR_STATE_UNSUPPORTED;
+ if (asic_type < CHIP_VEGA10 || asic_type == CHIP_ARCTURUS)
+ *states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
if (asic_type < CHIP_VEGA20)
- attr->states = ATTR_STATE_UNSUPPORTED;
+ *states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_dpm_pcie)) {
if (asic_type == CHIP_ARCTURUS)
- attr->states = ATTR_STATE_UNSUPPORTED;
+ *states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
- attr->states = ATTR_STATE_UNSUPPORTED;
+ *states = ATTR_STATE_UNSUPPORTED;
if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
(!is_support_sw_smu(adev) && hwmgr->od_enabled))
- attr->states = ATTR_STATE_UNSUPPORTED;
+ *states = ATTR_STATE_SUPPORTED;
} else if (DEVICE_ATTR_IS(mem_busy_percent)) {
if (adev->flags & AMD_IS_APU || asic_type == CHIP_VEGA10)
- attr->states = ATTR_STATE_UNSUPPORTED;
+ *states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pcie_bw)) {
/* PCIe Perf counters won't work on APU nodes */
if (adev->flags & AMD_IS_APU)
- attr->states = ATTR_STATE_UNSUPPORTED;
+ *states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(unique_id)) {
if (!adev->unique_id)
- attr->states = ATTR_STATE_UNSUPPORTED;
+ *states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_features)) {
- if (adev->flags & AMD_IS_APU || asic_type <= CHIP_VEGA10)
- attr->states = ATTR_STATE_UNSUPPORTED;
+ if (adev->flags & AMD_IS_APU || asic_type < CHIP_VEGA10)
+ *states = ATTR_STATE_UNSUPPORTED;
}
if (asic_type == CHIP_ARCTURUS) {
static int amdgpu_device_attr_create(struct amdgpu_device *adev,
struct amdgpu_device_attr *attr,
- uint32_t mask)
+ uint32_t mask, struct list_head *attr_list)
{
int ret = 0;
struct device_attribute *dev_attr = &attr->dev_attr;
const char *name = dev_attr->attr.name;
+ enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED;
+ struct amdgpu_device_attr_entry *attr_entry;
+
int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
- uint32_t mask) = default_attr_update;
+ uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update;
BUG_ON(!attr);
attr_update = attr->attr_update ? attr_update : default_attr_update;
- ret = attr_update(adev, attr, mask);
+ ret = attr_update(adev, attr, mask, &attr_states);
if (ret) {
dev_err(adev->dev, "failed to update device file %s, ret = %d\n",
name, ret);
return ret;
}
- /* the attr->states maybe changed after call attr->attr_update function */
- if (attr->states == ATTR_STATE_UNSUPPORTED)
+ if (attr_states == ATTR_STATE_UNSUPPORTED)
return 0;
ret = device_create_file(adev->dev, dev_attr);
name, ret);
}
- attr->states = ATTR_STATE_SUPPORTED;
+ attr_entry = kmalloc(sizeof(*attr_entry), GFP_KERNEL);
+ if (!attr_entry)
+ return -ENOMEM;
+
+ attr_entry->attr = attr;
+ INIT_LIST_HEAD(&attr_entry->entry);
+
+ list_add_tail(&attr_entry->entry, attr_list);
return ret;
}
{
struct device_attribute *dev_attr = &attr->dev_attr;
- if (attr->states == ATTR_STATE_UNSUPPORTED)
- return;
-
device_remove_file(adev->dev, dev_attr);
-
- attr->states = ATTR_STATE_UNSUPPORTED;
}
+static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
+ struct list_head *attr_list);
+
static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev,
struct amdgpu_device_attr *attrs,
uint32_t counts,
- uint32_t mask)
+ uint32_t mask,
+ struct list_head *attr_list)
{
int ret = 0;
uint32_t i = 0;
for (i = 0; i < counts; i++) {
- ret = amdgpu_device_attr_create(adev, &attrs[i], mask);
+ ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list);
if (ret)
goto failed;
}
return 0;
failed:
- for (; i > 0; i--) {
- amdgpu_device_attr_remove(adev, &attrs[i]);
- }
+ amdgpu_device_attr_remove_groups(adev, attr_list);
return ret;
}
static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
- struct amdgpu_device_attr *attrs,
- uint32_t counts)
+ struct list_head *attr_list)
{
- uint32_t i = 0;
+ struct amdgpu_device_attr_entry *entry, *entry_tmp;
- for (i = 0; i < counts; i++)
- amdgpu_device_attr_remove(adev, &attrs[i]);
+ if (list_empty(attr_list))
+ return ;
+
+ list_for_each_entry_safe(entry, entry_tmp, attr_list, entry) {
+ amdgpu_device_attr_remove(adev, entry->attr);
+ list_del(&entry->entry);
+ kfree(entry);
+ }
}
static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
int channel = to_sensor_dev_attr(attr)->index;
int r, temp = 0, size = sizeof(temp);
+ if (adev->in_gpu_reset)
+ return -EPERM;
+
if (channel >= PP_TEMP_MAX)
return -EINVAL;
u32 pwm_mode = 0;
int ret;
+ if (adev->in_gpu_reset)
+ return -EPERM;
+
ret = pm_runtime_get_sync(adev->ddev->dev);
if (ret < 0)
return ret;
int err, ret;
int value;
+ if (adev->in_gpu_reset)
+ return -EPERM;
+
err = kstrtoint(buf, 10, &value);
if (err)
return err;
u32 value;
u32 pwm_mode;
+ if (adev->in_gpu_reset)
+ return -EPERM;
+
err = pm_runtime_get_sync(adev->ddev->dev);
if (err < 0)
return err;
int err;
u32 speed = 0;
+ if (adev->in_gpu_reset)
+ return -EPERM;
+
err = pm_runtime_get_sync(adev->ddev->dev);
if (err < 0)
return err;
int err;
u32 speed = 0;
+ if (adev->in_gpu_reset)
+ return -EPERM;
+
err = pm_runtime_get_sync(adev->ddev->dev);
if (err < 0)
return err;
u32 size = sizeof(min_rpm);
int r;
+ if (adev->in_gpu_reset)
+ return -EPERM;
+
r = pm_runtime_get_sync(adev->ddev->dev);
if (r < 0)
return r;
u32 size = sizeof(max_rpm);
int r;
+ if (adev->in_gpu_reset)
+ return -EPERM;
+
r = pm_runtime_get_sync(adev->ddev->dev);
if (r < 0)
return r;
int err;
u32 rpm = 0;
+ if (adev->in_gpu_reset)
+ return -EPERM;
+
err = pm_runtime_get_sync(adev->ddev->dev);
if (err < 0)
return err;
u32 value;
u32 pwm_mode;
+ if (adev->in_gpu_reset)
+ return -EPERM;
+
err = pm_runtime_get_sync(adev->ddev->dev);
if (err < 0)
return err;
u32 pwm_mode = 0;
int ret;
+ if (adev->in_gpu_reset)
+ return -EPERM;
+
ret = pm_runtime_get_sync(adev->ddev->dev);
if (ret < 0)
return ret;
int value;
u32 pwm_mode;
+ if (adev->in_gpu_reset)
+ return -EPERM;
+
err = kstrtoint(buf, 10, &value);
if (err)
return err;
u32 vddgfx;
int r, size = sizeof(vddgfx);
+ if (adev->in_gpu_reset)
+ return -EPERM;
+
r = pm_runtime_get_sync(adev->ddev->dev);
if (r < 0)
return r;
u32 vddnb;
int r, size = sizeof(vddnb);
+ if (adev->in_gpu_reset)
+ return -EPERM;
+
/* only APUs have vddnb */
if (!(adev->flags & AMD_IS_APU))
return -EINVAL;
int r, size = sizeof(u32);
unsigned uw;
+ if (adev->in_gpu_reset)
+ return -EPERM;
+
r = pm_runtime_get_sync(adev->ddev->dev);
if (r < 0)
return r;
ssize_t size;
int r;
+ if (adev->in_gpu_reset)
+ return -EPERM;
+
r = pm_runtime_get_sync(adev->ddev->dev);
if (r < 0)
return r;
ssize_t size;
int r;
+ if (adev->in_gpu_reset)
+ return -EPERM;
+
r = pm_runtime_get_sync(adev->ddev->dev);
if (r < 0)
return r;
int err;
u32 value;
+ if (adev->in_gpu_reset)
+ return -EPERM;
+
if (amdgpu_sriov_vf(adev))
return -EINVAL;
uint32_t sclk;
int r, size = sizeof(sclk);
+ if (adev->in_gpu_reset)
+ return -EPERM;
+
r = pm_runtime_get_sync(adev->ddev->dev);
if (r < 0)
return r;
uint32_t mclk;
int r, size = sizeof(mclk);
+ if (adev->in_gpu_reset)
+ return -EPERM;
+
r = pm_runtime_get_sync(adev->ddev->dev);
if (r < 0)
return r;
if (adev->pm.dpm_enabled == 0)
return 0;
+ INIT_LIST_HEAD(&adev->pm.pm_attr_list);
+
adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
DRIVER_NAME, adev,
hwmon_groups);
ret = amdgpu_device_attr_create_groups(adev,
amdgpu_device_attrs,
ARRAY_SIZE(amdgpu_device_attrs),
- mask);
+ mask,
+ &adev->pm.pm_attr_list);
if (ret)
return ret;
if (adev->pm.int_hwmon_dev)
hwmon_device_unregister(adev->pm.int_hwmon_dev);
- amdgpu_device_attr_remove_groups(adev,
- amdgpu_device_attrs,
- ARRAY_SIZE(amdgpu_device_attrs));
+ amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list);
}
void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
u32 flags = 0;
int r;
+ if (adev->in_gpu_reset)
+ return -EPERM;
+
r = pm_runtime_get_sync(dev->dev);
if (r < 0)
return r;