drm/amdgpu: expand sdma copy_buffer interface with tmz parameter

[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_object.c

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index e3f16b4..c687f54 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -31,6 +31,7 @@
  */
 #include <linux/list.h>
 #include <linux/slab.h>
+#include <linux/dma-buf.h>
 
 #include <drm/amdgpu_drm.h>
 #include <drm/drm_cache.h>
@@ -925,6 +926,9 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
                return 0;
        }
 
+       if (bo->tbo.base.import_attach)
+               dma_buf_pin(bo->tbo.base.import_attach);
+
        bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
        /* force to pin into visible video ram */
        if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS))
@@ -1008,6 +1012,9 @@ int amdgpu_bo_unpin(struct amdgpu_bo *bo)
 
        amdgpu_bo_subtract_pin_size(bo);
 
+       if (bo->tbo.base.import_attach)
+               dma_buf_unpin(bo->tbo.base.import_attach);
+
        for (i = 0; i < bo->placement.num_placement; i++) {
                bo->placements[i].lpfn = 0;
                bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
@@ -1274,6 +1281,10 @@ void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
 
        amdgpu_bo_kunmap(abo);
 
+       if (abo->tbo.base.dma_buf && !abo->tbo.base.import_attach &&
+           bo->mem.mem_type != TTM_PL_SYSTEM)
+               dma_buf_move_notify(abo->tbo.base.dma_buf);
+
        /* remember the eviction */
        if (evict)
                atomic64_inc(&adev->num_evictions);
@@ -1307,6 +1318,12 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo)
        if (abo->kfd_bo)
                amdgpu_amdkfd_unreserve_memory_limit(abo);
 
+       /* We only remove the fence if the resv has individualized. */
+       WARN_ON_ONCE(bo->type == ttm_bo_type_kernel
+                       && bo->base.resv != &bo->base._resv);
+       if (bo->base.resv == &bo->base._resv)
+               amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo);
+
        if (bo->mem.mem_type != TTM_PL_VRAM || !bo->mem.mm_node ||
            !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE))
                return;
@@ -1403,29 +1420,51 @@ void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
 }
 
 /**
- * amdgpu_sync_wait_resv - Wait for BO reservation fences
+ * amdgpu_bo_sync_wait_resv - Wait for BO reservation fences
  *
- * @bo: buffer object
+ * @adev: amdgpu device pointer
+ * @resv: reservation object to sync to
+ * @sync_mode: synchronization mode
  * @owner: fence owner
  * @intr: Whether the wait is interruptible
  *
+ * Extract the fences from the reservation object and waits for them to finish.
+ *
  * Returns:
  * 0 on success, errno otherwise.
  */
-int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr)
+int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv,
+                            enum amdgpu_sync_mode sync_mode, void *owner,
+                            bool intr)
 {
-       struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
        struct amdgpu_sync sync;
        int r;
 
        amdgpu_sync_create(&sync);
-       amdgpu_sync_resv(adev, &sync, bo->tbo.base.resv, owner, false);
+       amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner);
        r = amdgpu_sync_wait(&sync, intr);
        amdgpu_sync_free(&sync);
-
        return r;
 }
 
+/**
+ * amdgpu_bo_sync_wait - Wrapper for amdgpu_bo_sync_wait_resv
+ * @bo: buffer object to wait for
+ * @owner: fence owner
+ * @intr: Whether the wait is interruptible
+ *
+ * Wrapper to wait for fences in a BO.
+ * Returns:
+ * 0 on success, errno otherwise.
+ */
+int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr)
+{
+       struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+
+       return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv,
+                                       AMDGPU_SYNC_NE_OWNER, owner, intr);
+}
+
 /**
  * amdgpu_bo_gpu_offset - return GPU offset of bo
  * @bo:        amdgpu object for which we query the offset