drm/sched: Convert the GPU scheduler to variable number of run-queues
[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_device.c
index e77f048..1507423 100644 (file)
@@ -885,13 +885,20 @@ static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
  */
 static int amdgpu_device_asic_init(struct amdgpu_device *adev)
 {
+       int ret;
+
        amdgpu_asic_pre_asic_init(adev);
 
        if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3) ||
-           adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0))
-               return amdgpu_atomfirmware_asic_init(adev, true);
-       else
+           adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0)) {
+               amdgpu_psp_wait_for_bootloader(adev);
+               ret = amdgpu_atomfirmware_asic_init(adev, true);
+               return ret;
+       } else {
                return amdgpu_atom_asic_init(adev->mode_info.atom_context);
+       }
+
+       return 0;
 }
 
 /**
@@ -1237,32 +1244,6 @@ bool amdgpu_device_need_post(struct amdgpu_device *adev)
        return true;
 }
 
-/*
- * On APUs with >= 64GB white flickering has been observed w/ SG enabled.
- * Disable S/G on such systems until we have a proper fix.
- * https://gitlab.freedesktop.org/drm/amd/-/issues/2354
- * https://gitlab.freedesktop.org/drm/amd/-/issues/2735
- */
-bool amdgpu_sg_display_supported(struct amdgpu_device *adev)
-{
-       switch (amdgpu_sg_display) {
-       case -1:
-               break;
-       case 0:
-               return false;
-       case 1:
-               return true;
-       default:
-               return false;
-       }
-       if ((totalram_pages() << (PAGE_SHIFT - 10)) +
-           (adev->gmc.real_vram_size / 1024) >= 64000000) {
-               DRM_WARN("Disabling S/G due to >=64GB RAM\n");
-               return false;
-       }
-       return true;
-}
-
 /*
  * Intel hosts such as Raptor Lake and Sapphire Rapids don't support dynamic
  * speed switching. Until we have confirmation from Intel that a specific host
@@ -2299,6 +2280,7 @@ static int amdgpu_device_init_schedulers(struct amdgpu_device *adev)
                }
 
                r = drm_sched_init(&ring->sched, &amdgpu_sched_ops,
+                                  DRM_SCHED_PRIORITY_COUNT,
                                   ring->num_hw_submission, 0,
                                   timeout, adev->reset_domain->wq,
                                   ring->sched_score, ring->name,
@@ -4694,9 +4676,12 @@ int amdgpu_device_mode1_reset(struct amdgpu_device *adev)
        }
 
        if (ret)
-               dev_err(adev->dev, "GPU mode1 reset failed\n");
+               goto mode1_reset_failed;
 
        amdgpu_device_load_pci_state(adev->pdev);
+       ret = amdgpu_psp_wait_for_bootloader(adev);
+       if (ret)
+               goto mode1_reset_failed;
 
        /* wait for asic to come out of reset */
        for (i = 0; i < adev->usec_timeout; i++) {
@@ -4707,7 +4692,17 @@ int amdgpu_device_mode1_reset(struct amdgpu_device *adev)
                udelay(1);
        }
 
+       if (i >= adev->usec_timeout) {
+               ret = -ETIMEDOUT;
+               goto mode1_reset_failed;
+       }
+
        amdgpu_atombios_scratch_regs_engine_hung(adev, false);
+
+       return 0;
+
+mode1_reset_failed:
+       dev_err(adev->dev, "GPU mode1 reset failed\n");
        return ret;
 }
 
@@ -4849,7 +4844,7 @@ static void amdgpu_reset_capture_coredumpm(struct amdgpu_device *adev)
        struct drm_device *dev = adev_to_drm(adev);
 
        ktime_get_ts64(&adev->reset_time);
-       dev_coredumpm(dev->dev, THIS_MODULE, adev, 0, GFP_KERNEL,
+       dev_coredumpm(dev->dev, THIS_MODULE, adev, 0, GFP_NOWAIT,
                      amdgpu_devcoredump_read, amdgpu_devcoredump_free);
 }
 #endif