drm/amdgpu: remove duplicate magic constants from amdgpu_amdkfd_gfx*.c

[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_amdkfd_gfx_v7.c

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
index 1a0a5f7..5254562 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
@@ -29,6 +29,7 @@
 #include "cikd.h"
 #include "cik_sdma.h"
 #include "amdgpu_ucode.h"
+#include "gfx_v7_0.h"
 #include "gca/gfx_7_2_d.h"
 #include "gca/gfx_7_2_enum.h"
 #include "gca/gfx_7_2_sh_mask.h"
@@ -38,8 +39,6 @@
 #include "gmc/gmc_7_1_sh_mask.h"
 #include "cik_structs.h"
 
-#define CIK_PIPE_PER_MEC       (4)
-
 enum {
        MAX_TRAPID = 8,         /* 3 bits in the bitfield. */
        MAX_WATCH_ADDRESSES = 4
@@ -185,8 +184,10 @@ static void unlock_srbm(struct kgd_dev *kgd)
 static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id,
                                uint32_t queue_id)
 {
-       uint32_t mec = (++pipe_id / CIK_PIPE_PER_MEC) + 1;
-       uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC);
+       struct amdgpu_device *adev = get_amdgpu_device(kgd);
+
+       uint32_t mec = (++pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
+       uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
 
        lock_srbm(kgd, mec, pipe, queue_id, 0);
 }
@@ -243,18 +244,7 @@ static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
 static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
                                uint32_t hpd_size, uint64_t hpd_gpu_addr)
 {
-       struct amdgpu_device *adev = get_amdgpu_device(kgd);
-
-       uint32_t mec = (++pipe_id / CIK_PIPE_PER_MEC) + 1;
-       uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC);
-
-       lock_srbm(kgd, mec, pipe, 0, 0);
-       WREG32(mmCP_HPD_EOP_BASE_ADDR, lower_32_bits(hpd_gpu_addr >> 8));
-       WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(hpd_gpu_addr >> 8));
-       WREG32(mmCP_HPD_EOP_VMID, 0);
-       WREG32(mmCP_HPD_EOP_CONTROL, hpd_size);
-       unlock_srbm(kgd);
-
+       /* amdgpu owns the per-pipe state */
        return 0;
 }
 
@@ -264,8 +254,8 @@ static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
        uint32_t mec;
        uint32_t pipe;
 
-       mec = (pipe_id / CIK_PIPE_PER_MEC) + 1;
-       pipe = (pipe_id % CIK_PIPE_PER_MEC);
+       mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
+       pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
 
        lock_srbm(kgd, mec, pipe, 0, 0);
 
@@ -309,55 +299,11 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
        m = get_mqd(mqd);
 
        is_wptr_shadow_valid = !get_user(wptr_shadow, wptr);
-
-       acquire_queue(kgd, pipe_id, queue_id);
-       WREG32(mmCP_MQD_BASE_ADDR, m->cp_mqd_base_addr_lo);
-       WREG32(mmCP_MQD_BASE_ADDR_HI, m->cp_mqd_base_addr_hi);
-       WREG32(mmCP_MQD_CONTROL, m->cp_mqd_control);
-
-       WREG32(mmCP_HQD_PQ_BASE, m->cp_hqd_pq_base_lo);
-       WREG32(mmCP_HQD_PQ_BASE_HI, m->cp_hqd_pq_base_hi);
-       WREG32(mmCP_HQD_PQ_CONTROL, m->cp_hqd_pq_control);
-
-       WREG32(mmCP_HQD_IB_CONTROL, m->cp_hqd_ib_control);
-       WREG32(mmCP_HQD_IB_BASE_ADDR, m->cp_hqd_ib_base_addr_lo);
-       WREG32(mmCP_HQD_IB_BASE_ADDR_HI, m->cp_hqd_ib_base_addr_hi);
-
-       WREG32(mmCP_HQD_IB_RPTR, m->cp_hqd_ib_rptr);
-
-       WREG32(mmCP_HQD_PERSISTENT_STATE, m->cp_hqd_persistent_state);
-       WREG32(mmCP_HQD_SEMA_CMD, m->cp_hqd_sema_cmd);
-       WREG32(mmCP_HQD_MSG_TYPE, m->cp_hqd_msg_type);
-
-       WREG32(mmCP_HQD_ATOMIC0_PREOP_LO, m->cp_hqd_atomic0_preop_lo);
-       WREG32(mmCP_HQD_ATOMIC0_PREOP_HI, m->cp_hqd_atomic0_preop_hi);
-       WREG32(mmCP_HQD_ATOMIC1_PREOP_LO, m->cp_hqd_atomic1_preop_lo);
-       WREG32(mmCP_HQD_ATOMIC1_PREOP_HI, m->cp_hqd_atomic1_preop_hi);
-
-       WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR, m->cp_hqd_pq_rptr_report_addr_lo);
-       WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
-                       m->cp_hqd_pq_rptr_report_addr_hi);
-
-       WREG32(mmCP_HQD_PQ_RPTR, m->cp_hqd_pq_rptr);
-
-       WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, m->cp_hqd_pq_wptr_poll_addr_lo);
-       WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, m->cp_hqd_pq_wptr_poll_addr_hi);
-
-       WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, m->cp_hqd_pq_doorbell_control);
-
-       WREG32(mmCP_HQD_VMID, m->cp_hqd_vmid);
-
-       WREG32(mmCP_HQD_QUANTUM, m->cp_hqd_quantum);
-
-       WREG32(mmCP_HQD_PIPE_PRIORITY, m->cp_hqd_pipe_priority);
-       WREG32(mmCP_HQD_QUEUE_PRIORITY, m->cp_hqd_queue_priority);
-
-       WREG32(mmCP_HQD_IQ_RPTR, m->cp_hqd_iq_rptr);
-
        if (is_wptr_shadow_valid)
-               WREG32(mmCP_HQD_PQ_WPTR, wptr_shadow);
+               m->cp_hqd_pq_wptr = wptr_shadow;
 
-       WREG32(mmCP_HQD_ACTIVE, m->cp_hqd_active);
+       acquire_queue(kgd, pipe_id, queue_id);
+       gfx_v7_0_mqd_commit(adev, m);
        release_queue(kgd);
 
        return 0;