drm/amdkfd: replace kgd_dev in various kfd2kgd funcs

[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_amdkfd_gfx_v10_3.c

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
index 2fc7dfc..9804309 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
@@ -79,14 +79,12 @@ static void release_queue(struct amdgpu_device *adev)
        unlock_srbm(adev);
 }
 
-static void program_sh_mem_settings_v10_3(struct kgd_dev *kgd, uint32_t vmid,
+static void program_sh_mem_settings_v10_3(struct amdgpu_device *adev, uint32_t vmid,
                                        uint32_t sh_mem_config,
                                        uint32_t sh_mem_ape1_base,
                                        uint32_t sh_mem_ape1_limit,
                                        uint32_t sh_mem_bases)
 {
-       struct amdgpu_device *adev = get_amdgpu_device(kgd);
-
        lock_srbm(adev, 0, 0, 0, vmid);
 
        WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
@@ -97,11 +95,9 @@ static void program_sh_mem_settings_v10_3(struct kgd_dev *kgd, uint32_t vmid,
 }
 
 /* ATC is defeatured on Sienna_Cichlid */
-static int set_pasid_vmid_mapping_v10_3(struct kgd_dev *kgd, unsigned int pasid,
+static int set_pasid_vmid_mapping_v10_3(struct amdgpu_device *adev, unsigned int pasid,
                                        unsigned int vmid)
 {
-       struct amdgpu_device *adev = get_amdgpu_device(kgd);
-
        uint32_t value = pasid << IH_VMID_0_LUT__PASID__SHIFT;
 
        /* Mapping vmid to pasid also for IH block */
@@ -112,9 +108,8 @@ static int set_pasid_vmid_mapping_v10_3(struct kgd_dev *kgd, unsigned int pasid,
        return 0;
 }
 
-static int init_interrupts_v10_3(struct kgd_dev *kgd, uint32_t pipe_id)
+static int init_interrupts_v10_3(struct amdgpu_device *adev, uint32_t pipe_id)
 {
-       struct amdgpu_device *adev = get_amdgpu_device(kgd);
        uint32_t mec;
        uint32_t pipe;
 
@@ -593,12 +588,12 @@ static int hqd_sdma_destroy_v10_3(struct amdgpu_device *adev, void *mqd,
 }
 
 
-static int address_watch_disable_v10_3(struct kgd_dev *kgd)
+static int address_watch_disable_v10_3(struct amdgpu_device *adev)
 {
        return 0;
 }
 
-static int address_watch_execute_v10_3(struct kgd_dev *kgd,
+static int address_watch_execute_v10_3(struct amdgpu_device *adev,
                                        unsigned int watch_point_id,
                                        uint32_t cntl_val,
                                        uint32_t addr_hi,
@@ -607,11 +602,10 @@ static int address_watch_execute_v10_3(struct kgd_dev *kgd,
        return 0;
 }
 
-static int wave_control_execute_v10_3(struct kgd_dev *kgd,
+static int wave_control_execute_v10_3(struct amdgpu_device *adev,
                                        uint32_t gfx_index_val,
                                        uint32_t sq_cmd)
 {
-       struct amdgpu_device *adev = get_amdgpu_device(kgd);
        uint32_t data = 0;
 
        mutex_lock(&adev->grbm_idx_mutex);
@@ -632,27 +626,23 @@ static int wave_control_execute_v10_3(struct kgd_dev *kgd,
        return 0;
 }
 
-static uint32_t address_watch_get_offset_v10_3(struct kgd_dev *kgd,
+static uint32_t address_watch_get_offset_v10_3(struct amdgpu_device *adev,
                                        unsigned int watch_point_id,
                                        unsigned int reg_offset)
 {
        return 0;
 }
 
-static void set_vm_context_page_table_base_v10_3(struct kgd_dev *kgd, uint32_t vmid,
-               uint64_t page_table_base)
+static void set_vm_context_page_table_base_v10_3(struct amdgpu_device *adev,
+               uint32_t vmid, uint64_t page_table_base)
 {
-       struct amdgpu_device *adev = get_amdgpu_device(kgd);
-
        /* SDMA is on gfxhub as well for Navi1* series */
        adev->gfxhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base);
 }
 
-static void program_trap_handler_settings_v10_3(struct kgd_dev *kgd,
+static void program_trap_handler_settings_v10_3(struct amdgpu_device *adev,
                        uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr)
 {
-       struct amdgpu_device *adev = get_amdgpu_device(kgd);
-
        lock_srbm(adev, 0, 0, 0, vmid);
 
        /*
@@ -676,11 +666,10 @@ static void program_trap_handler_settings_v10_3(struct kgd_dev *kgd,
 }
 
 #if 0
-uint32_t enable_debug_trap_v10_3(struct kgd_dev *kgd,
+uint32_t enable_debug_trap_v10_3(struct amdgpu_device *adev,
                                uint32_t trap_debug_wave_launch_mode,
                                uint32_t vmid)
 {
-       struct amdgpu_device *adev = get_amdgpu_device(kgd);
        uint32_t data = 0;
        uint32_t orig_wave_cntl_value;
        uint32_t orig_stall_vmid;
@@ -707,10 +696,8 @@ uint32_t enable_debug_trap_v10_3(struct kgd_dev *kgd,
        return 0;
 }
 
-uint32_t disable_debug_trap_v10_3(struct kgd_dev *kgd)
+uint32_t disable_debug_trap_v10_3(struct amdgpu_device *adev)
 {
-       struct amdgpu_device *adev = get_amdgpu_device(kgd);
-
        mutex_lock(&adev->grbm_idx_mutex);
 
        WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
@@ -720,11 +707,10 @@ uint32_t disable_debug_trap_v10_3(struct kgd_dev *kgd)
        return 0;
 }
 
-uint32_t set_wave_launch_trap_override_v10_3(struct kgd_dev *kgd,
+uint32_t set_wave_launch_trap_override_v10_3(struct amdgpu_device *adev,
                                                uint32_t trap_override,
                                                uint32_t trap_mask)
 {
-       struct amdgpu_device *adev = get_amdgpu_device(kgd);
        uint32_t data = 0;
 
        mutex_lock(&adev->grbm_idx_mutex);
@@ -749,11 +735,10 @@ uint32_t set_wave_launch_trap_override_v10_3(struct kgd_dev *kgd,
        return 0;
 }
 
-uint32_t set_wave_launch_mode_v10_3(struct kgd_dev *kgd,
+uint32_t set_wave_launch_mode_v10_3(struct amdgpu_device *adev,
                                        uint8_t wave_launch_mode,
                                        uint32_t vmid)
 {
-       struct amdgpu_device *adev = get_amdgpu_device(kgd);
        uint32_t data = 0;
        bool is_stall_mode;
        bool is_mode_set;
@@ -792,16 +777,14 @@ uint32_t set_wave_launch_mode_v10_3(struct kgd_dev *kgd,
  *     sem_rearm_wait_time      -- Wait Count for Semaphore re-arm.
  *     deq_retry_wait_time      -- Wait Count for Global Wave Syncs.
  */
-void get_iq_wait_times_v10_3(struct kgd_dev *kgd,
+void get_iq_wait_times_v10_3(struct amdgpu_device *adev,
                                        uint32_t *wait_times)
 
 {
-       struct amdgpu_device *adev = get_amdgpu_device(kgd);
-
        *wait_times = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_IQ_WAIT_TIME2));
 }
 
-void build_grace_period_packet_info_v10_3(struct kgd_dev *kgd,
+void build_grace_period_packet_info_v10_3(struct amdgpu_device *adev,
                                                uint32_t wait_times,
                                                uint32_t grace_period,
                                                uint32_t *reg_offset,