drm/amdkfd: Add XCC instance to kgd2kfd interface (v3)

[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_amdkfd_gfx_v10_3.c

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
index 5c4152a..52d0d35 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
@@ -80,7 +80,7 @@ static void program_sh_mem_settings_v10_3(struct amdgpu_device *adev, uint32_t v
                                        uint32_t sh_mem_config,
                                        uint32_t sh_mem_ape1_base,
                                        uint32_t sh_mem_ape1_limit,
-                                       uint32_t sh_mem_bases)
+                                       uint32_t sh_mem_bases, uint32_t inst)
 {
        lock_srbm(adev, 0, 0, 0, vmid);
 
@@ -93,7 +93,7 @@ static void program_sh_mem_settings_v10_3(struct amdgpu_device *adev, uint32_t v
 
 /* ATC is defeatured on Sienna_Cichlid */
 static int set_pasid_vmid_mapping_v10_3(struct amdgpu_device *adev, unsigned int pasid,
-                                       unsigned int vmid)
+                                       unsigned int vmid, uint32_t inst)
 {
        uint32_t value = pasid << IH_VMID_0_LUT__PASID__SHIFT;
 
@@ -105,7 +105,8 @@ static int set_pasid_vmid_mapping_v10_3(struct amdgpu_device *adev, unsigned int
        return 0;
 }
 
-static int init_interrupts_v10_3(struct amdgpu_device *adev, uint32_t pipe_id)
+static int init_interrupts_v10_3(struct amdgpu_device *adev, uint32_t pipe_id,
+                               uint32_t inst)
 {
        uint32_t mec;
        uint32_t pipe;
@@ -177,7 +178,7 @@ static inline struct v10_sdma_mqd *get_sdma_mqd(void *mqd)
 static int hqd_load_v10_3(struct amdgpu_device *adev, void *mqd,
                        uint32_t pipe_id, uint32_t queue_id,
                        uint32_t __user *wptr, uint32_t wptr_shift,
-                       uint32_t wptr_mask, struct mm_struct *mm)
+                       uint32_t wptr_mask, struct mm_struct *mm, uint32_t inst)
 {
        struct v10_compute_mqd *m;
        uint32_t *mqd_hqd;
@@ -273,7 +274,7 @@ static int hqd_load_v10_3(struct amdgpu_device *adev, void *mqd,
 
 static int hiq_mqd_load_v10_3(struct amdgpu_device *adev, void *mqd,
                            uint32_t pipe_id, uint32_t queue_id,
-                           uint32_t doorbell_off)
+                           uint32_t doorbell_off, uint32_t inst)
 {
        struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring;
        struct v10_compute_mqd *m;
@@ -325,7 +326,7 @@ out_unlock:
 
 static int hqd_dump_v10_3(struct amdgpu_device *adev,
                        uint32_t pipe_id, uint32_t queue_id,
-                       uint32_t (**dump)[2], uint32_t *n_regs)
+                       uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst)
 {
        uint32_t i = 0, reg;
 #define HQD_N_REGS 56
@@ -456,7 +457,7 @@ static int hqd_sdma_dump_v10_3(struct amdgpu_device *adev,
 
 static bool hqd_is_occupied_v10_3(struct amdgpu_device *adev,
                                uint64_t queue_address, uint32_t pipe_id,
-                               uint32_t queue_id)
+                               uint32_t queue_id, uint32_t inst)
 {
        uint32_t act;
        bool retval = false;
@@ -498,7 +499,7 @@ static bool hqd_sdma_is_occupied_v10_3(struct amdgpu_device *adev,
 static int hqd_destroy_v10_3(struct amdgpu_device *adev, void *mqd,
                                enum kfd_preempt_type reset_type,
                                unsigned int utimeout, uint32_t pipe_id,
-                               uint32_t queue_id)
+                               uint32_t queue_id, uint32_t inst)
 {
        enum hqd_dequeue_request_type type;
        unsigned long end_jiffies;
@@ -586,7 +587,7 @@ static int hqd_sdma_destroy_v10_3(struct amdgpu_device *adev, void *mqd,
 
 static int wave_control_execute_v10_3(struct amdgpu_device *adev,
                                        uint32_t gfx_index_val,
-                                       uint32_t sq_cmd)
+                                       uint32_t sq_cmd, uint32_t inst)
 {
        uint32_t data = 0;
 
@@ -628,7 +629,8 @@ static void set_vm_context_page_table_base_v10_3(struct amdgpu_device *adev,
 }
 
 static void program_trap_handler_settings_v10_3(struct amdgpu_device *adev,
-                       uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr)
+                       uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr,
+                       uint32_t inst)
 {
        lock_srbm(adev, 0, 0, 0, vmid);
 
@@ -765,7 +767,7 @@ uint32_t set_wave_launch_mode_v10_3(struct amdgpu_device *adev,
  *     deq_retry_wait_time      -- Wait Count for Global Wave Syncs.
  */
 void get_iq_wait_times_v10_3(struct amdgpu_device *adev,
-                                       uint32_t *wait_times)
+                                       uint32_t *wait_times, uint32_t inst)
 
 {
        *wait_times = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_IQ_WAIT_TIME2));
@@ -775,7 +777,8 @@ void build_grace_period_packet_info_v10_3(struct amdgpu_device *adev,
                                                uint32_t wait_times,
                                                uint32_t grace_period,
                                                uint32_t *reg_offset,
-                                               uint32_t *reg_data)
+                                               uint32_t *reg_data,
+                                               uint32_t inst)
 {
        *reg_data = wait_times;