Merge tag 'gpio-updates-for-v5.11' of git://git.kernel.org/pub/scm/linux/kernel/git...

[linux-2.6-microblaze.git] / drivers / gpio / gpio-sifive.c

diff --git a/drivers/gpio/gpio-sifive.c b/drivers/gpio/gpio-sifive.c
index c7d47e4..403f9e8 100644 (file)
--- a/drivers/gpio/gpio-sifive.c
+++ b/drivers/gpio/gpio-sifive.c
@@ -29,7 +29,6 @@
 #define SIFIVE_GPIO_OUTPUT_XOR 0x40
 
 #define SIFIVE_GPIO_MAX                32
-#define SIFIVE_GPIO_IRQ_OFFSET 7
 
 struct sifive_gpio {
        void __iomem            *base;
@@ -37,7 +36,7 @@ struct sifive_gpio {
        struct regmap           *regs;
        unsigned long           irq_state;
        unsigned int            trigger[SIFIVE_GPIO_MAX];
-       unsigned int            irq_parent[SIFIVE_GPIO_MAX];
+       unsigned int            irq_number[SIFIVE_GPIO_MAX];
 };
 
 static void sifive_gpio_set_ie(struct sifive_gpio *chip, unsigned int offset)
@@ -155,8 +154,12 @@ static int sifive_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
                                             unsigned int *parent,
                                             unsigned int *parent_type)
 {
+       struct sifive_gpio *chip = gpiochip_get_data(gc);
+       struct irq_data *d = irq_get_irq_data(chip->irq_number[child]);
+
        *parent_type = IRQ_TYPE_NONE;
-       *parent = child + SIFIVE_GPIO_IRQ_OFFSET;
+       *parent = irqd_to_hwirq(d);
+
        return 0;
 }
 
@@ -176,7 +179,7 @@ static int sifive_gpio_probe(struct platform_device *pdev)
        struct irq_domain *parent;
        struct gpio_irq_chip *girq;
        struct sifive_gpio *chip;
-       int ret, ngpio;
+       int ret, ngpio, i;
 
        chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
        if (!chip)
@@ -211,6 +214,9 @@ static int sifive_gpio_probe(struct platform_device *pdev)
                return -ENODEV;
        }
 
+       for (i = 0; i < ngpio; i++)
+               chip->irq_number[i] = platform_get_irq(pdev, i);
+
        ret = bgpio_init(&chip->gc, dev, 4,
                         chip->base + SIFIVE_GPIO_INPUT_VAL,
                         chip->base + SIFIVE_GPIO_OUTPUT_VAL,