Merge git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-edac

[linux-2.6-microblaze.git] / drivers / edac / i7core_edac.c

diff --git a/drivers/edac/i7core_edac.c b/drivers/edac/i7core_edac.c
index 6d89c78..d27778f 100644 (file)
--- a/drivers/edac/i7core_edac.c
+++ b/drivers/edac/i7core_edac.c
@@ -90,7 +90,7 @@ MODULE_PARM_DESC(use_pci_fixup, "Enable PCI fixup to seek for hidden devices");
 #define MC_MAX_DOD     0x64
 
 /*
- * OFFSETS for Device 3 Function 4, as inicated on Xeon 5500 datasheet:
+ * OFFSETS for Device 3 Function 4, as indicated on Xeon 5500 datasheet:
  * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
  */
 
@@ -101,7 +101,7 @@ MODULE_PARM_DESC(use_pci_fixup, "Enable PCI fixup to seek for hidden devices");
   #define DIMM1_COR_ERR(r)                     (((r) >> 16) & 0x7fff)
   #define DIMM0_COR_ERR(r)                     ((r) & 0x7fff)
 
-/* OFFSETS for Device 3 Function 2, as inicated on Xeon 5500 datasheet */
+/* OFFSETS for Device 3 Function 2, as indicated on Xeon 5500 datasheet */
 #define MC_SSRCONTROL          0x48
   #define SSR_MODE_DISABLE     0x00
   #define SSR_MODE_ENABLE      0x01
@@ -221,7 +221,9 @@ struct i7core_inject {
 };
 
 struct i7core_channel {
-       u32             ranks;
+       bool            is_3dimms_present;
+       bool            is_single_4rank;
+       bool            has_4rank;
        u32             dimms;
 };
 
@@ -397,7 +399,7 @@ static DEFINE_PCI_DEVICE_TABLE(i7core_pci_tbl) = {
 };
 
 /****************************************************************************
-                       Anciliary status routines
+                       Ancillary status routines
  ****************************************************************************/
 
        /* MC_CONTROL bits */
@@ -555,21 +557,20 @@ static int get_dimm_config(struct mem_ctl_info *mci)
                pci_read_config_dword(pvt->pci_ch[i][0],
                                MC_CHANNEL_DIMM_INIT_PARAMS, &data);
 
-               pvt->channel[i].ranks = (data & QUAD_RANK_PRESENT) ?
-                                               4 : 2;
+
+               if (data & THREE_DIMMS_PRESENT)
+                       pvt->channel[i].is_3dimms_present = true;
+
+               if (data & SINGLE_QUAD_RANK_PRESENT)
+                       pvt->channel[i].is_single_4rank = true;
+
+               if (data & QUAD_RANK_PRESENT)
+                       pvt->channel[i].has_4rank = true;
 
                if (data & REGISTERED_DIMM)
                        mtype = MEM_RDDR3;
                else
                        mtype = MEM_DDR3;
-#if 0
-               if (data & THREE_DIMMS_PRESENT)
-                       pvt->channel[i].dimms = 3;
-               else if (data & SINGLE_QUAD_RANK_PRESENT)
-                       pvt->channel[i].dimms = 1;
-               else
-                       pvt->channel[i].dimms = 2;
-#endif
 
                /* Devices 4-6 function 1 */
                pci_read_config_dword(pvt->pci_ch[i][1],
@@ -580,11 +581,13 @@ static int get_dimm_config(struct mem_ctl_info *mci)
                                MC_DOD_CH_DIMM2, &dimm_dod[2]);
 
                debugf0("Ch%d phy rd%d, wr%d (0x%08x): "
-                       "%d ranks, %cDIMMs\n",
+                       "%s%s%s%cDIMMs\n",
                        i,
                        RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i),
                        data,
-                       pvt->channel[i].ranks,
+                       pvt->channel[i].is_3dimms_present ? "3DIMMS " : "",
+                       pvt->channel[i].is_3dimms_present ? "SINGLE_4R " : "",
+                       pvt->channel[i].has_4rank ? "HAS_4R " : "",
                        (data & REGISTERED_DIMM) ? 'R' : 'U');
 
                for (j = 0; j < 3; j++) {
@@ -1243,7 +1246,7 @@ static int i7core_get_onedevice(struct pci_dev **prev,
                              dev_descr->dev_id, *prev);
 
        /*
-        * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core regs
+        * On Xeon 55xx, the Intel QuickPath Arch Generic Non-core regs
         * is at addr 8086:2c40, instead of 8086:2c41. So, we need
         * to probe for the alternate address in case of failure
         */
@@ -1623,7 +1626,7 @@ static void i7core_mce_output_error(struct mem_ctl_info *mci,
                                    const struct mce *m)
 {
        struct i7core_pvt *pvt = mci->pvt_info;
-       char *type, *optype, *err, *msg;
+       char *type, *optype, *err, msg[80];
        enum hw_event_mc_err_type tp_event;
        unsigned long error = m->status & 0x1ff0000l;
        bool uncorrected_error = m->mcgstatus & 1ll << 61;
@@ -1701,10 +1704,7 @@ static void i7core_mce_output_error(struct mem_ctl_info *mci,
                err = "unknown";
        }
 
-       msg = kasprintf(GFP_ATOMIC,
-               "addr=0x%08llx cpu=%d count=%d Err=%08llx:%08llx (%s: %s))\n",
-               (long long) m->addr, m->cpu, core_err_cnt,
-               (long long)m->status, (long long)m->misc, optype, err);
+       snprintf(msg, sizeof(msg), "count=%d %s", core_err_cnt, optype);
 
        /*
         * Call the helper to output message
@@ -1718,8 +1718,6 @@ static void i7core_mce_output_error(struct mem_ctl_info *mci,
                                     syndrome,
                                     channel, dimm, -1,
                                     err, msg, m);
-
-       kfree(msg);
 }
 
 /*
@@ -2016,7 +2014,7 @@ static int set_sdram_scrub_rate(struct mem_ctl_info *mci, u32 new_bw)
 
 /*
  * get_sdram_scrub_rate                This routine convert current scrub rate value
- *                             into byte/sec bandwidth accourding to
+ *                             into byte/sec bandwidth according to
  *                             SCRUBINTERVAL formula found in datasheet.
  */
 static int get_sdram_scrub_rate(struct mem_ctl_info *mci)