Merge tag 'nfs-for-4.20-5' of git://git.linux-nfs.org/projects/trondmy/linux-nfs

[linux-2.6-microblaze.git] / drivers / edac / amd64_edac.c

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 18aeabb..6ea9857 100644 (file)
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -211,7 +211,7 @@ static int __set_scrub_rate(struct amd64_pvt *pvt, u32 new_bw, u32 min_rate)
 
        scrubval = scrubrates[i].scrubval;
 
-       if (pvt->fam == 0x17) {
+       if (pvt->fam == 0x17 || pvt->fam == 0x18) {
                __f17h_set_scrubval(pvt, scrubval);
        } else if (pvt->fam == 0x15 && pvt->model == 0x60) {
                f15h_select_dct(pvt, 0);
@@ -264,6 +264,7 @@ static int get_scrub_rate(struct mem_ctl_info *mci)
                break;
 
        case 0x17:
+       case 0x18:
                amd64_read_pci_cfg(pvt->F6, F17H_SCR_BASE_ADDR, &scrubval);
                if (scrubval & BIT(0)) {
                        amd64_read_pci_cfg(pvt->F6, F17H_SCR_LIMIT_ADDR, &scrubval);
@@ -1044,6 +1045,7 @@ static void determine_memory_type(struct amd64_pvt *pvt)
                goto ddr3;
 
        case 0x17:
+       case 0x18:
                if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(5))
                        pvt->dram_type = MEM_LRDDR4;
                else if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(4))
@@ -2200,6 +2202,15 @@ static struct amd64_family_type family_types[] = {
                        .dbam_to_cs             = f17_base_addr_to_cs_size,
                }
        },
+       [F17_M10H_CPUS] = {
+               .ctl_name = "F17h_M10h",
+               .f0_id = PCI_DEVICE_ID_AMD_17H_M10H_DF_F0,
+               .f6_id = PCI_DEVICE_ID_AMD_17H_M10H_DF_F6,
+               .ops = {
+                       .early_channel_count    = f17_early_channel_count,
+                       .dbam_to_cs             = f17_base_addr_to_cs_size,
+               }
+       },
 };
 
 /*
@@ -3188,8 +3199,18 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt)
                break;
 
        case 0x17:
+               if (pvt->model >= 0x10 && pvt->model <= 0x2f) {
+                       fam_type = &family_types[F17_M10H_CPUS];
+                       pvt->ops = &family_types[F17_M10H_CPUS].ops;
+                       break;
+               }
+               /* fall through */
+       case 0x18:
                fam_type        = &family_types[F17_CPUS];
                pvt->ops        = &family_types[F17_CPUS].ops;
+
+               if (pvt->fam == 0x18)
+                       family_types[F17_CPUS].ctl_name = "F18h";
                break;
 
        default:
@@ -3428,6 +3449,7 @@ static const struct x86_cpu_id amd64_cpuids[] = {
        { X86_VENDOR_AMD, 0x15, X86_MODEL_ANY,  X86_FEATURE_ANY, 0 },
        { X86_VENDOR_AMD, 0x16, X86_MODEL_ANY,  X86_FEATURE_ANY, 0 },
        { X86_VENDOR_AMD, 0x17, X86_MODEL_ANY,  X86_FEATURE_ANY, 0 },
+       { X86_VENDOR_HYGON, 0x18, X86_MODEL_ANY, X86_FEATURE_ANY, 0 },
        { }
 };
 MODULE_DEVICE_TABLE(x86cpu, amd64_cpuids);