struct clk *dma_clk;
spinlock_t global_lock;
void __iomem *base_addr;
- struct tegra_dma_chip_data *chip_data;
+ const struct tegra_dma_chip_data *chip_data;
/* Some register need to be cache before suspend */
u32 reg_gen;
}
/* Tegra20 specific DMA controller information */
-static struct tegra_dma_chip_data tegra20_dma_chip_data = {
+static const struct tegra_dma_chip_data tegra20_dma_chip_data = {
.nr_channels = 16,
.max_dma_count = 1024UL * 64,
};
#if defined(CONFIG_OF)
/* Tegra30 specific DMA controller information */
-static struct tegra_dma_chip_data tegra30_dma_chip_data = {
+static const struct tegra_dma_chip_data tegra30_dma_chip_data = {
.nr_channels = 32,
.max_dma_count = 1024UL * 64,
};
struct tegra_dma *tdma;
int ret;
int i;
- struct tegra_dma_chip_data *cdata = NULL;
+ const struct tegra_dma_chip_data *cdata = NULL;
if (pdev->dev.of_node) {
const struct of_device_id *match;