Merge tag 'folio-5.18d' of git://git.infradead.org/users/willy/pagecache

[linux-2.6-microblaze.git] / drivers / dma / dw-axi-dmac / dw-axi-dmac-platform.c

diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 33baf15..e9c9bcb 100644 (file)
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier:  GPL-2.0
+// SPDX-License-Identifier: GPL-2.0
 // (C) 2017-2018 Synopsys, Inc. (www.synopsys.com)
 
 /*
@@ -35,7 +35,7 @@
 /*
  * The set of bus widths supported by the DMA controller. DW AXI DMAC supports
  * master data bus width up to 512 bits (for both AXI master interfaces), but
- * it depends on IP block configurarion.
+ * it depends on IP block configuration.
  */
 #define AXI_DMA_BUSWIDTHS                \
        (DMA_SLAVE_BUSWIDTH_1_BYTE      | \
@@ -1089,10 +1089,10 @@ static irqreturn_t dw_axi_dma_interrupt(int irq, void *dev_id)
 
        u32 status, i;
 
-       /* Disable DMAC inerrupts. We'll enable them after processing chanels */
+       /* Disable DMAC interrupts. We'll enable them after processing channels */
        axi_dma_irq_disable(chip);
 
-       /* Poll, clear and process every chanel interrupt status */
+       /* Poll, clear and process every channel interrupt status */
        for (i = 0; i < dw->hdata->nr_channels; i++) {
                chan = &dw->chan[i];
                status = axi_chan_irq_read(chan);