crypto: hisilicon - add ZIP device using mode parameter

[linux-2.6-microblaze.git] / drivers / crypto / hisilicon / zip / zip_main.c

diff --git a/drivers/crypto/hisilicon/zip/zip_main.c b/drivers/crypto/hisilicon/zip/zip_main.c
index 4fb5a32..9cdecff 100644 (file)
--- a/drivers/crypto/hisilicon/zip/zip_main.c
+++ b/drivers/crypto/hisilicon/zip/zip_main.c
@@ -211,6 +211,19 @@ static const struct debugfs_reg32 hzip_dfx_regs[] = {
        {"HZIP_DECOMP_LZ77_CURR_ST       ",  0x9cull},
 };
 
+static const struct kernel_param_ops zip_uacce_mode_ops = {
+       .set = uacce_mode_set,
+       .get = param_get_int,
+};
+
+/*
+ * uacce_mode = 0 means zip only register to crypto,
+ * uacce_mode = 1 means zip both register to crypto and uacce.
+ */
+static u32 uacce_mode = UACCE_MODE_NOUACCE;
+module_param_cb(uacce_mode, &zip_uacce_mode_ops, &uacce_mode, 0444);
+MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC);
+
 static int pf_q_num_set(const char *val, const struct kernel_param *kp)
 {
        return q_num_set(val, kp, PCI_DEVICE_ID_ZIP_PF);
@@ -752,6 +765,7 @@ static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
        qm->pdev = pdev;
        qm->ver = pdev->revision;
        qm->algs = "zlib\ngzip";
+       qm->mode = uacce_mode;
        qm->sqe_size = HZIP_SQE_SIZE;
        qm->dev_name = hisi_zip_name;