Merge tag 'block-5.10-2020-10-30' of git://git.kernel.dk/linux-block

[linux-2.6-microblaze.git] / drivers / cpufreq / s3c2440-cpufreq.c

diff --git a/drivers/cpufreq/s3c2440-cpufreq.c b/drivers/cpufreq/s3c2440-cpufreq.c
index 3f772ba..148e8ae 100644 (file)
--- a/drivers/cpufreq/s3c2440-cpufreq.c
+++ b/drivers/cpufreq/s3c2440-cpufreq.c
@@ -20,14 +20,27 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/io.h>
+#include <linux/soc/samsung/s3c-cpufreq-core.h>
+#include <linux/soc/samsung/s3c-pm.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <mach/regs-clock.h>
+#define S3C2440_CLKDIVN_PDIVN       (1<<0)
+#define S3C2440_CLKDIVN_HDIVN_MASK   (3<<1)
+#define S3C2440_CLKDIVN_HDIVN_1      (0<<1)
+#define S3C2440_CLKDIVN_HDIVN_2      (1<<1)
+#define S3C2440_CLKDIVN_HDIVN_4_8    (2<<1)
+#define S3C2440_CLKDIVN_HDIVN_3_6    (3<<1)
+#define S3C2440_CLKDIVN_UCLK         (1<<3)
 
-#include <plat/cpu.h>
-#include <plat/cpu-freq-core.h>
+#define S3C2440_CAMDIVN_CAMCLK_MASK  (0xf<<0)
+#define S3C2440_CAMDIVN_CAMCLK_SEL   (1<<4)
+#define S3C2440_CAMDIVN_HCLK3_HALF   (1<<8)
+#define S3C2440_CAMDIVN_HCLK4_HALF   (1<<9)
+#define S3C2440_CAMDIVN_DVSEN        (1<<12)
+
+#define S3C2442_CAMDIVN_CAMCLK_DIV3  (1<<5)
 
 static struct clk *xtal;
 static struct clk *fclk;
@@ -143,8 +156,8 @@ static void s3c2440_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
        s3c_freq_dbg("%s: divisors: h=%d, p=%d\n", __func__,
                     cfg->divs.h_divisor, cfg->divs.p_divisor);
 
-       clkdiv = __raw_readl(S3C2410_CLKDIVN);
-       camdiv = __raw_readl(S3C2440_CAMDIVN);
+       clkdiv = s3c24xx_read_clkdivn();
+       camdiv = s3c2440_read_camdivn();
 
        clkdiv &= ~(S3C2440_CLKDIVN_HDIVN_MASK | S3C2440_CLKDIVN_PDIVN);
        camdiv &= ~CAMDIVN_HCLK_HALF;
@@ -184,11 +197,11 @@ static void s3c2440_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
         * then make a short delay and remove the hclk halving if necessary.
         */
 
-       __raw_writel(camdiv | CAMDIVN_HCLK_HALF, S3C2440_CAMDIVN);
-       __raw_writel(clkdiv, S3C2410_CLKDIVN);
+       s3c2440_write_camdivn(camdiv | CAMDIVN_HCLK_HALF);
+       s3c24xx_write_clkdivn(clkdiv);
 
        ndelay(20);
-       __raw_writel(camdiv, S3C2440_CAMDIVN);
+       s3c2440_write_camdivn(camdiv);
 
        clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk);
 }