Merge branch 'for-4.2/ti-clk-move' of https://github.com/t-kristo/linux-pm into clk...

[linux-2.6-microblaze.git] / drivers / clk / ti / dpll44xx.c

diff --git a/drivers/clk/ti/dpll44xx.c b/drivers/clk/ti/dpll44xx.c
index ef1a5b4..73af77a 100644 (file)
--- a/drivers/clk/ti/dpll44xx.c
+++ b/drivers/clk/ti/dpll44xx.c
@@ -192,42 +192,36 @@ out:
 /**
  * omap4_dpll_regm4xen_determine_rate - determine rate for a DPLL
  * @hw: pointer to the clock to determine rate for
- * @rate: target rate for the DPLL
- * @best_parent_rate: pointer for returning best parent rate
- * @best_parent_clk: pointer for returning best parent clock
+ * @req: target rate request
  *
  * Determines which DPLL mode to use for reaching a desired rate.
  * Checks whether the DPLL shall be in bypass or locked mode, and if
  * locked, calculates the M,N values for the DPLL via round-rate.
- * Returns a positive clock rate with success, negative error value
- * in failure.
+ * Returns 0 on success and a negative error value otherwise.
  */
-long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate,
-                                       unsigned long min_rate,
-                                       unsigned long max_rate,
-                                       unsigned long *best_parent_rate,
-                                       struct clk_hw **best_parent_clk)
+int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
+                                      struct clk_rate_request *req)
 {
        struct clk_hw_omap *clk = to_clk_hw_omap(hw);
        struct dpll_data *dd;
 
-       if (!hw || !rate)
+       if (!req->rate)
                return -EINVAL;
 
        dd = clk->dpll_data;
        if (!dd)
                return -EINVAL;
 
-       if (__clk_get_rate(dd->clk_bypass) == rate &&
+       if (__clk_get_rate(dd->clk_bypass) == req->rate &&
            (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
-               *best_parent_clk = __clk_get_hw(dd->clk_bypass);
+               req->best_parent_hw = __clk_get_hw(dd->clk_bypass);
        } else {
-               rate = omap4_dpll_regm4xen_round_rate(hw, rate,
-                                                     best_parent_rate);
-               *best_parent_clk = __clk_get_hw(dd->clk_ref);
+               req->rate = omap4_dpll_regm4xen_round_rate(hw, req->rate,
+                                               &req->best_parent_rate);
+               req->best_parent_hw = __clk_get_hw(dd->clk_ref);
        }
 
-       *best_parent_rate = rate;
+       req->best_parent_rate = req->rate;
 
-       return rate;
+       return 0;
 }