clk: agilex/stratix10: add support for the 2nd bypass

[linux-2.6-microblaze.git] / drivers / clk / socfpga / stratix10-clk.h

diff --git a/drivers/clk/socfpga/stratix10-clk.h b/drivers/clk/socfpga/stratix10-clk.h
index 420deed..75234e0 100644 (file)
--- a/drivers/clk/socfpga/stratix10-clk.h
+++ b/drivers/clk/socfpga/stratix10-clk.h
@@ -7,7 +7,7 @@
 #define        __STRATIX10_CLK_H
 
 struct stratix10_clock_data {
-       struct clk_onecell_data clk_data;
+       struct clk_hw_onecell_data      clk_data;
        void __iomem            *base;
 };
 
@@ -71,18 +71,20 @@ struct stratix10_gate_clock {
        u8                      fixed_div;
 };
 
-struct clk *s10_register_pll(const struct stratix10_pll_clock *,
-                            void __iomem *);
-struct clk *agilex_register_pll(const struct stratix10_pll_clock *,
-                               void __iomem *);
-struct clk *n5x_register_pll(const struct stratix10_pll_clock *clks,
+struct clk_hw *s10_register_pll(const struct stratix10_pll_clock *clks,
                             void __iomem *reg);
-struct clk *s10_register_periph(const struct stratix10_perip_c_clock *,
+struct clk_hw *agilex_register_pll(const struct stratix10_pll_clock *clks,
                                void __iomem *reg);
-struct clk *n5x_register_periph(const struct n5x_perip_c_clock *clks,
+struct clk_hw *n5x_register_pll(const struct stratix10_pll_clock *clks,
+                            void __iomem *reg);
+struct clk_hw *s10_register_periph(const struct stratix10_perip_c_clock *clks,
+                               void __iomem *reg);
+struct clk_hw *n5x_register_periph(const struct n5x_perip_c_clock *clks,
                                void __iomem *reg);
-struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *,
-                                   void __iomem *);
-struct clk *s10_register_gate(const struct stratix10_gate_clock *,
-                             void __iomem *);
+struct clk_hw *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *clks,
+                                   void __iomem *reg);
+struct clk_hw *s10_register_gate(const struct stratix10_gate_clock *clks,
+                             void __iomem *reg);
+struct clk_hw *agilex_register_gate(const struct stratix10_gate_clock *clks,
+                             void __iomem *reg);
 #endif /* __STRATIX10_CLK_H */