Merge tag 'microblaze-v5.13' of git://git.monstr.eu/linux-2.6-microblaze

[linux-2.6-microblaze.git] / drivers / clk / socfpga / clk-pll-s10.c

diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pll-s10.c
index f6f66e0..70076a8 100644 (file)
--- a/drivers/clk/socfpga/clk-pll-s10.c
+++ b/drivers/clk/socfpga/clk-pll-s10.c
@@ -107,7 +107,7 @@ static unsigned long clk_boot_clk_recalc_rate(struct clk_hw *hwclk,
                                         unsigned long parent_rate)
 {
        struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
-       u32 div = 1;
+       u32 div;
 
        div = ((readl(socfpgaclk->hw.reg) &
                SWCTRLBTCLKSEL_MASK) >>
@@ -187,13 +187,14 @@ static const struct clk_ops clk_boot_ops = {
        .prepare = clk_pll_prepare,
 };
 
-struct clk *s10_register_pll(const struct stratix10_pll_clock *clks,
+struct clk_hw *s10_register_pll(const struct stratix10_pll_clock *clks,
                             void __iomem *reg)
 {
-       struct clk *clk;
+       struct clk_hw *hw_clk;
        struct socfpga_pll *pll_clk;
        struct clk_init_data init;
        const char *name = clks->name;
+       int ret;
 
        pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
        if (WARN_ON(!pll_clk))
@@ -216,21 +217,24 @@ struct clk *s10_register_pll(const struct stratix10_pll_clock *clks,
 
        pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
 
-       clk = clk_register(NULL, &pll_clk->hw.hw);
-       if (WARN_ON(IS_ERR(clk))) {
+       hw_clk = &pll_clk->hw.hw;
+
+       ret = clk_hw_register(NULL, hw_clk);
+       if (ret) {
                kfree(pll_clk);
-               return NULL;
+               return ERR_PTR(ret);
        }
-       return clk;
+       return hw_clk;
 }
 
-struct clk *agilex_register_pll(const struct stratix10_pll_clock *clks,
+struct clk_hw *agilex_register_pll(const struct stratix10_pll_clock *clks,
                                void __iomem *reg)
 {
-       struct clk *clk;
+       struct clk_hw *hw_clk;
        struct socfpga_pll *pll_clk;
        struct clk_init_data init;
        const char *name = clks->name;
+       int ret;
 
        pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
        if (WARN_ON(!pll_clk))
@@ -252,22 +256,24 @@ struct clk *agilex_register_pll(const struct stratix10_pll_clock *clks,
        pll_clk->hw.hw.init = &init;
 
        pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
+       hw_clk = &pll_clk->hw.hw;
 
-       clk = clk_register(NULL, &pll_clk->hw.hw);
-       if (WARN_ON(IS_ERR(clk))) {
+       ret = clk_hw_register(NULL, hw_clk);
+       if (ret) {
                kfree(pll_clk);
-               return NULL;
+               return ERR_PTR(ret);
        }
-       return clk;
+       return hw_clk;
 }
 
-struct clk *n5x_register_pll(const struct stratix10_pll_clock *clks,
+struct clk_hw *n5x_register_pll(const struct stratix10_pll_clock *clks,
                             void __iomem *reg)
 {
-       struct clk *clk;
+       struct clk_hw *hw_clk;
        struct socfpga_pll *pll_clk;
        struct clk_init_data init;
        const char *name = clks->name;
+       int ret;
 
        pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
        if (WARN_ON(!pll_clk))
@@ -289,11 +295,12 @@ struct clk *n5x_register_pll(const struct stratix10_pll_clock *clks,
        pll_clk->hw.hw.init = &init;
 
        pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
+       hw_clk = &pll_clk->hw.hw;
 
-       clk = clk_register(NULL, &pll_clk->hw.hw);
-       if (WARN_ON(IS_ERR(clk))) {
+       ret = clk_hw_register(NULL, hw_clk);
+       if (ret) {
                kfree(pll_clk);
-               return NULL;
+               return ERR_PTR(ret);
        }
-       return clk;
+       return hw_clk;
 }