clk: rockchip: convert pclk_wdt boilerplat to new SGRF_GATE macro

[linux-2.6-microblaze.git] / drivers / clk / rockchip / clk-rk3368.c

diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index d239bbc..6ecc17b 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -820,6 +820,9 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
        GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 2, GFLAGS),
        GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 1, GFLAGS),
 
+       /* Watchdog pclk is controlled by sgrf_soc_con3[7]. */
+       SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_pd_alive"),
+
        /*
         * pclk_vio gates
         * pclk_vio comes from the exactly same source as hclk_vio
@@ -871,7 +874,6 @@ static void __init rk3368_clk_init(struct device_node *np)
 {
        struct rockchip_clk_provider *ctx;
        void __iomem *reg_base;
-       struct clk *clk;
 
        reg_base = of_iomap(np, 0);
        if (!reg_base) {
@@ -886,14 +888,6 @@ static void __init rk3368_clk_init(struct device_node *np)
                return;
        }
 
-       /* Watchdog pclk is controlled by sgrf_soc_con3[7]. */
-       clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1);
-       if (IS_ERR(clk))
-               pr_warn("%s: could not register clock pclk_wdt: %ld\n",
-                       __func__, PTR_ERR(clk));
-       else
-               rockchip_clk_add_lookup(ctx, clk, PCLK_WDT);
-
        rockchip_clk_register_plls(ctx, rk3368_pll_clks,
                                   ARRAY_SIZE(rk3368_pll_clks),
                                   RK3368_GRF_SOC_STATUS0);