clk: rockchip: convert rk3036 pll type to use internal lock status

[linux-2.6-microblaze.git] / drivers / clk / rockchip / clk-pll.c

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 945f8b2..4c6c916 100644 (file)
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -12,6 +12,7 @@
 #include <linux/io.h>
 #include <linux/delay.h>
 #include <linux/clk-provider.h>
+#include <linux/iopoll.h>
 #include <linux/regmap.h>
 #include <linux/clk.h>
 #include "clk.h"
@@ -109,12 +110,31 @@ static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)
 #define RK3036_PLLCON1_REFDIV_SHIFT            0
 #define RK3036_PLLCON1_POSTDIV2_MASK           0x7
 #define RK3036_PLLCON1_POSTDIV2_SHIFT          6
+#define RK3036_PLLCON1_LOCK_STATUS             BIT(10)
 #define RK3036_PLLCON1_DSMPD_MASK              0x1
 #define RK3036_PLLCON1_DSMPD_SHIFT             12
+#define RK3036_PLLCON1_PWRDOWN                 BIT(13)
 #define RK3036_PLLCON2_FRAC_MASK               0xffffff
 #define RK3036_PLLCON2_FRAC_SHIFT              0
 
-#define RK3036_PLLCON1_PWRDOWN                 (1 << 13)
+static int rockchip_rk3036_pll_wait_lock(struct rockchip_clk_pll *pll)
+{
+       u32 pllcon;
+       int ret;
+
+       /*
+        * Lock time typical 250, max 500 input clock cycles @24MHz
+        * So define a very safe maximum of 1000us, meaning 24000 cycles.
+        */
+       ret = readl_relaxed_poll_timeout(pll->reg_base + RK3036_PLLCON(1),
+                                        pllcon,
+                                        pllcon & RK3036_PLLCON1_LOCK_STATUS,
+                                        0, 1000);
+       if (ret)
+               pr_err("%s: timeout waiting for pll to lock\n", __func__);
+
+       return ret;
+}
 
 static void rockchip_rk3036_pll_get_params(struct rockchip_clk_pll *pll,
                                        struct rockchip_pll_rate_table *rate)
@@ -212,7 +232,7 @@ static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll,
        writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2));
 
        /* wait for the pll to lock */
-       ret = rockchip_pll_wait_lock(pll);
+       ret = rockchip_rk3036_pll_wait_lock(pll);
        if (ret) {
                pr_warn("%s: pll update unsuccessful, trying to restore old params\n",
                        __func__);
@@ -251,7 +271,7 @@ static int rockchip_rk3036_pll_enable(struct clk_hw *hw)
 
        writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0),
               pll->reg_base + RK3036_PLLCON(1));
-       rockchip_pll_wait_lock(pll);
+       rockchip_rk3036_pll_wait_lock(pll);
 
        return 0;
 }