Merge v5.14-rc3 into usb-next

[linux-2.6-microblaze.git] / drivers / clk / renesas / r9a07g044-cpg.c

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 50b5269..ae24e03 100644 (file)
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -30,8 +30,9 @@ enum clk_ids {
        CLK_PLL2_DIV20,
        CLK_PLL3,
        CLK_PLL3_DIV2,
+       CLK_PLL3_DIV2_4,
+       CLK_PLL3_DIV2_4_2,
        CLK_PLL3_DIV4,
-       CLK_PLL3_DIV8,
        CLK_PLL4,
        CLK_PLL5,
        CLK_PLL5_DIV2,
@@ -42,12 +43,13 @@ enum clk_ids {
 };
 
 /* Divider tables */
-static const struct clk_div_table dtable_3b[] = {
+static const struct clk_div_table dtable_1_32[] = {
        {0, 1},
        {1, 2},
        {2, 4},
        {3, 8},
        {4, 32},
+       {0, 0},
 };
 
 static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
@@ -66,47 +68,56 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
        DEF_FIXED(".pll2_div20", CLK_PLL2_DIV20, CLK_PLL2, 1, 20),
 
        DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
+       DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
+       DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
        DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4),
-       DEF_FIXED(".pll3_div8", CLK_PLL3_DIV8, CLK_PLL3, 1, 8),
 
        /* Core output clk */
        DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1),
        DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A,
-               dtable_3b, CLK_DIVIDER_HIWORD_MASK),
+               dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
        DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1),
-       DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV8,
-               DIVPL3B, dtable_3b, CLK_DIVIDER_HIWORD_MASK),
+       DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4,
+               DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
+       DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2,
+               DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
 };
 
 static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
-       DEF_MOD("gic",          R9A07G044_CLK_GIC600,
-                               R9A07G044_CLK_P1,
-                               0x514, BIT(0), (BIT(0) | BIT(1))),
-       DEF_MOD("ia55",         R9A07G044_CLK_IA55,
-                               R9A07G044_CLK_P1,
-                               0x518, (BIT(0) | BIT(1)), BIT(0)),
-       DEF_MOD("scif0",        R9A07G044_CLK_SCIF0,
-                               R9A07G044_CLK_P0,
-                               0x584, BIT(0), BIT(0)),
-       DEF_MOD("scif1",        R9A07G044_CLK_SCIF1,
-                               R9A07G044_CLK_P0,
-                               0x584, BIT(1), BIT(1)),
-       DEF_MOD("scif2",        R9A07G044_CLK_SCIF2,
-                               R9A07G044_CLK_P0,
-                               0x584, BIT(2), BIT(2)),
-       DEF_MOD("scif3",        R9A07G044_CLK_SCIF3,
-                               R9A07G044_CLK_P0,
-                               0x584, BIT(3), BIT(3)),
-       DEF_MOD("scif4",        R9A07G044_CLK_SCIF4,
-                               R9A07G044_CLK_P0,
-                               0x584, BIT(4), BIT(4)),
-       DEF_MOD("sci0",         R9A07G044_CLK_SCI0,
-                               R9A07G044_CLK_P0,
-                               0x588, BIT(0), BIT(0)),
+       DEF_MOD("gic",          R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1,
+                               0x514, 0),
+       DEF_MOD("ia55_pclk",    R9A07G044_IA55_PCLK, R9A07G044_CLK_P2,
+                               0x518, 0),
+       DEF_MOD("ia55_clk",     R9A07G044_IA55_CLK, R9A07G044_CLK_P1,
+                               0x518, 1),
+       DEF_MOD("scif0",        R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0,
+                               0x584, 0),
+       DEF_MOD("scif1",        R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0,
+                               0x584, 1),
+       DEF_MOD("scif2",        R9A07G044_SCIF2_CLK_PCK, R9A07G044_CLK_P0,
+                               0x584, 2),
+       DEF_MOD("scif3",        R9A07G044_SCIF3_CLK_PCK, R9A07G044_CLK_P0,
+                               0x584, 3),
+       DEF_MOD("scif4",        R9A07G044_SCIF4_CLK_PCK, R9A07G044_CLK_P0,
+                               0x584, 4),
+       DEF_MOD("sci0",         R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0,
+                               0x588, 0),
+};
+
+static struct rzg2l_reset r9a07g044_resets[] = {
+       DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0),
+       DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1),
+       DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
+       DEF_RST(R9A07G044_SCIF0_RST_SYSTEM_N, 0x884, 0),
+       DEF_RST(R9A07G044_SCIF1_RST_SYSTEM_N, 0x884, 1),
+       DEF_RST(R9A07G044_SCIF2_RST_SYSTEM_N, 0x884, 2),
+       DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3),
+       DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4),
+       DEF_RST(R9A07G044_SCI0_RST, 0x888, 0),
 };
 
 static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
-       MOD_CLK_BASE + R9A07G044_CLK_GIC600,
+       MOD_CLK_BASE + R9A07G044_GIC600_GICCLK,
 };
 
 const struct rzg2l_cpg_info r9a07g044_cpg_info = {
@@ -123,5 +134,9 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info = {
        /* Module Clocks */
        .mod_clks = r9a07g044_mod_clks,
        .num_mod_clks = ARRAY_SIZE(r9a07g044_mod_clks),
-       .num_hw_mod_clks = R9A07G044_CLK_MIPI_DSI_PIN + 1,
+       .num_hw_mod_clks = R9A07G044_TSU_PCLK + 1,
+
+       /* Resets */
+       .resets = r9a07g044_resets,
+       .num_resets = ARRAY_SIZE(r9a07g044_resets),
 };