clk: qcom: add read-only alpha pll post divider operations

[linux-2.6-microblaze.git] / drivers / clk / qcom / clk-alpha-pll.h

diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index d6e1ee2..7593e8a 100644 (file)
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -17,6 +17,30 @@
 #include <linux/clk-provider.h>
 #include "clk-regmap.h"
 
+/* Alpha PLL types */
+enum {
+       CLK_ALPHA_PLL_TYPE_DEFAULT,
+       CLK_ALPHA_PLL_TYPE_HUAYRA,
+       CLK_ALPHA_PLL_TYPE_BRAMMO,
+       CLK_ALPHA_PLL_TYPE_MAX,
+};
+
+enum {
+       PLL_OFF_L_VAL,
+       PLL_OFF_ALPHA_VAL,
+       PLL_OFF_ALPHA_VAL_U,
+       PLL_OFF_USER_CTL,
+       PLL_OFF_USER_CTL_U,
+       PLL_OFF_CONFIG_CTL,
+       PLL_OFF_CONFIG_CTL_U,
+       PLL_OFF_TEST_CTL,
+       PLL_OFF_TEST_CTL_U,
+       PLL_OFF_STATUS,
+       PLL_OFF_MAX_REGS
+};
+
+extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS];
+
 struct pll_vco {
        unsigned long min_freq;
        unsigned long max_freq;
@@ -27,16 +51,18 @@ struct pll_vco {
  * struct clk_alpha_pll - phase locked loop (PLL)
  * @offset: base address of registers
  * @vco_table: array of VCO settings
+ * @regs: alpha pll register map (see @clk_alpha_pll_regs)
  * @clkr: regmap clock handle
  */
 struct clk_alpha_pll {
        u32 offset;
+       const u8 *regs;
 
        const struct pll_vco *vco_table;
        size_t num_vco;
 #define SUPPORTS_OFFLINE_REQ   BIT(0)
-#define SUPPORTS_16BIT_ALPHA   BIT(1)
 #define SUPPORTS_FSM_MODE      BIT(2)
+#define SUPPORTS_DYNAMIC_UPDATE        BIT(3)
        u8 flags;
 
        struct clk_regmap clkr;
@@ -45,12 +71,14 @@ struct clk_alpha_pll {
 /**
  * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
  * @offset: base address of registers
+ * @regs: alpha pll register map (see @clk_alpha_pll_regs)
  * @width: width of post-divider
  * @clkr: regmap clock handle
  */
 struct clk_alpha_pll_postdiv {
        u32 offset;
        u8 width;
+       const u8 *regs;
 
        struct clk_regmap clkr;
 };
@@ -58,12 +86,15 @@ struct clk_alpha_pll_postdiv {
 struct alpha_pll_config {
        u32 l;
        u32 alpha;
+       u32 alpha_hi;
        u32 config_ctl_val;
        u32 config_ctl_hi_val;
        u32 main_output_mask;
        u32 aux_output_mask;
        u32 aux2_output_mask;
        u32 early_output_mask;
+       u32 alpha_en_mask;
+       u32 alpha_mode_mask;
        u32 pre_div_val;
        u32 pre_div_mask;
        u32 post_div_val;
@@ -75,6 +106,8 @@ struct alpha_pll_config {
 extern const struct clk_ops clk_alpha_pll_ops;
 extern const struct clk_ops clk_alpha_pll_hwfsm_ops;
 extern const struct clk_ops clk_alpha_pll_postdiv_ops;
+extern const struct clk_ops clk_alpha_pll_huayra_ops;
+extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops;
 
 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
                             const struct alpha_pll_config *config);