clk: core: replace clk_{readl,writel} with {readl,writel}

[linux-2.6-microblaze.git] / drivers / clk / nxp / clk-lpc18xx-cgu.c

diff --git a/drivers/clk/nxp/clk-lpc18xx-cgu.c b/drivers/clk/nxp/clk-lpc18xx-cgu.c
index 2531174..f5bc8bd 100644 (file)
--- a/drivers/clk/nxp/clk-lpc18xx-cgu.c
+++ b/drivers/clk/nxp/clk-lpc18xx-cgu.c
@@ -352,9 +352,9 @@ static unsigned long lpc18xx_pll0_recalc_rate(struct clk_hw *hw,
        struct lpc18xx_pll *pll = to_lpc_pll(hw);
        u32 ctrl, mdiv, msel, npdiv;
 
-       ctrl = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
-       mdiv = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_MDIV);
-       npdiv = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV);
+       ctrl = readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
+       mdiv = readl(pll->reg + LPC18XX_CGU_PLL0USB_MDIV);
+       npdiv = readl(pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV);
 
        if (ctrl & LPC18XX_PLL0_CTRL_BYPASS)
                return parent_rate;
@@ -415,25 +415,25 @@ static int lpc18xx_pll0_set_rate(struct clk_hw *hw, unsigned long rate,
        m |= lpc18xx_pll0_msel2seli(m) << LPC18XX_PLL0_MDIV_SELI_SHIFT;
 
        /* Power down PLL, disable clk output and dividers */
-       ctrl = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
+       ctrl = readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
        ctrl |= LPC18XX_PLL0_CTRL_PD;
        ctrl &= ~(LPC18XX_PLL0_CTRL_BYPASS | LPC18XX_PLL0_CTRL_DIRECTI |
                  LPC18XX_PLL0_CTRL_DIRECTO | LPC18XX_PLL0_CTRL_CLKEN);
-       clk_writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
+       writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
 
        /* Configure new PLL settings */
-       clk_writel(m, pll->reg + LPC18XX_CGU_PLL0USB_MDIV);
-       clk_writel(LPC18XX_PLL0_NP_DIVS_1, pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV);
+       writel(m, pll->reg + LPC18XX_CGU_PLL0USB_MDIV);
+       writel(LPC18XX_PLL0_NP_DIVS_1, pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV);
 
        /* Power up PLL and wait for lock */
        ctrl &= ~LPC18XX_PLL0_CTRL_PD;
-       clk_writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
+       writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
        do {
                udelay(10);
-               stat = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_STAT);
+               stat = readl(pll->reg + LPC18XX_CGU_PLL0USB_STAT);
                if (stat & LPC18XX_PLL0_STAT_LOCK) {
                        ctrl |= LPC18XX_PLL0_CTRL_CLKEN;
-                       clk_writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
+                       writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
 
                        return 0;
                }
@@ -458,8 +458,8 @@ static unsigned long lpc18xx_pll1_recalc_rate(struct clk_hw *hw,
        bool direct, fbsel;
        u32 stat, ctrl;
 
-       stat = clk_readl(pll->reg + LPC18XX_CGU_PLL1_STAT);
-       ctrl = clk_readl(pll->reg + LPC18XX_CGU_PLL1_CTRL);
+       stat = readl(pll->reg + LPC18XX_CGU_PLL1_STAT);
+       ctrl = readl(pll->reg + LPC18XX_CGU_PLL1_CTRL);
 
        direct = (ctrl & LPC18XX_PLL1_CTRL_DIRECT) ? true : false;
        fbsel = (ctrl & LPC18XX_PLL1_CTRL_FBSEL) ? true : false;