Merge tag 'backlight-next-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/lee...

[linux-2.6-microblaze.git] / drivers / clk / meson / axg.h

diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h
index 23ea879..624d8d3 100644 (file)
--- a/drivers/clk/meson/axg.h
+++ b/drivers/clk/meson/axg.h
@@ -102,67 +102,4 @@
 #define HHI_DPLL_TOP_I                 0x318
 #define HHI_DPLL_TOP2_I                        0x31C
 
-/*
- * CLKID index values
- *
- * These indices are entirely contrived and do not map onto the hardware.
- * It has now been decided to expose everything by default in the DT header:
- * include/dt-bindings/clock/axg-clkc.h. Only the clocks ids we don't want
- * to expose, such as the internal muxes and dividers of composite clocks,
- * will remain defined here.
- */
-#define CLKID_MPEG_SEL                         8
-#define CLKID_MPEG_DIV                         9
-#define CLKID_SD_EMMC_B_CLK0_SEL               61
-#define CLKID_SD_EMMC_B_CLK0_DIV               62
-#define CLKID_SD_EMMC_C_CLK0_SEL               63
-#define CLKID_SD_EMMC_C_CLK0_DIV               64
-#define CLKID_MPLL0_DIV                                65
-#define CLKID_MPLL1_DIV                                66
-#define CLKID_MPLL2_DIV                                67
-#define CLKID_MPLL3_DIV                                68
-#define CLKID_MPLL_PREDIV                      70
-#define CLKID_FCLK_DIV2_DIV                    71
-#define CLKID_FCLK_DIV3_DIV                    72
-#define CLKID_FCLK_DIV4_DIV                    73
-#define CLKID_FCLK_DIV5_DIV                    74
-#define CLKID_FCLK_DIV7_DIV                    75
-#define CLKID_PCIE_PLL                         76
-#define CLKID_PCIE_MUX                         77
-#define CLKID_PCIE_REF                         78
-#define CLKID_GEN_CLK_SEL                      82
-#define CLKID_GEN_CLK_DIV                      83
-#define CLKID_SYS_PLL_DCO                      85
-#define CLKID_FIXED_PLL_DCO                    86
-#define CLKID_GP0_PLL_DCO                      87
-#define CLKID_HIFI_PLL_DCO                     88
-#define CLKID_PCIE_PLL_DCO                     89
-#define CLKID_PCIE_PLL_OD                      90
-#define CLKID_VPU_0_DIV                                91
-#define CLKID_VPU_1_DIV                                94
-#define CLKID_VAPB_0_DIV                       98
-#define CLKID_VAPB_1_DIV                       101
-#define CLKID_VCLK_SEL                         108
-#define CLKID_VCLK2_SEL                                109
-#define CLKID_VCLK_INPUT                       110
-#define CLKID_VCLK2_INPUT                      111
-#define CLKID_VCLK_DIV                         112
-#define CLKID_VCLK2_DIV                                113
-#define CLKID_VCLK_DIV2_EN                     114
-#define CLKID_VCLK_DIV4_EN                     115
-#define CLKID_VCLK_DIV6_EN                     116
-#define CLKID_VCLK_DIV12_EN                    117
-#define CLKID_VCLK2_DIV2_EN                    118
-#define CLKID_VCLK2_DIV4_EN                    119
-#define CLKID_VCLK2_DIV6_EN                    120
-#define CLKID_VCLK2_DIV12_EN                   121
-#define CLKID_CTS_ENCL_SEL                     132
-#define CLKID_VDIN_MEAS_SEL                    134
-#define CLKID_VDIN_MEAS_DIV                    135
-
-#define NR_CLKS                                        137
-
-/* include the CLKIDs that have been made part of the DT binding */
-#include <dt-bindings/clock/axg-clkc.h>
-
 #endif /* __AXG_H */