Merge branches 'clk-ingenic', 'clk-mtk-mux', 'clk-qcom-sdm845-pcie', 'clk-mtk-crit...

[linux-2.6-microblaze.git] / drivers / clk / meson / axg.c

diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 792735d..7a8ef80 100644 (file)
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -9,16 +9,17 @@
  * Author: Qiufang Dai <qiufang.dai@amlogic.com>
  */
 
-#include <linux/clk.h>
 #include <linux/clk-provider.h>
 #include <linux/init.h>
 #include <linux/of_device.h>
-#include <linux/mfd/syscon.h>
 #include <linux/platform_device.h>
-#include <linux/regmap.h>
 
-#include "clkc.h"
+#include "clk-input.h"
+#include "clk-regmap.h"
+#include "clk-pll.h"
+#include "clk-mpll.h"
 #include "axg.h"
+#include "meson-eeclk.h"
 
 static DEFINE_SPINLOCK(meson_clk_lock);
 
@@ -58,7 +59,7 @@ static struct clk_regmap axg_fixed_pll_dco = {
        .hw.init = &(struct clk_init_data){
                .name = "fixed_pll_dco",
                .ops = &meson_clk_pll_ro_ops,
-               .parent_names = (const char *[]){ "xtal" },
+               .parent_names = (const char *[]){ IN_PREFIX "xtal" },
                .num_parents = 1,
        },
 };
@@ -113,7 +114,7 @@ static struct clk_regmap axg_sys_pll_dco = {
        .hw.init = &(struct clk_init_data){
                .name = "sys_pll_dco",
                .ops = &meson_clk_pll_ro_ops,
-               .parent_names = (const char *[]){ "xtal" },
+               .parent_names = (const char *[]){ IN_PREFIX "xtal" },
                .num_parents = 1,
        },
 };
@@ -214,7 +215,7 @@ static struct clk_regmap axg_gp0_pll_dco = {
        .hw.init = &(struct clk_init_data){
                .name = "gp0_pll_dco",
                .ops = &meson_clk_pll_ops,
-               .parent_names = (const char *[]){ "xtal" },
+               .parent_names = (const char *[]){ IN_PREFIX "xtal" },
                .num_parents = 1,
        },
 };
@@ -283,7 +284,7 @@ static struct clk_regmap axg_hifi_pll_dco = {
        .hw.init = &(struct clk_init_data){
                .name = "hifi_pll_dco",
                .ops = &meson_clk_pll_ops,
-               .parent_names = (const char *[]){ "xtal" },
+               .parent_names = (const char *[]){ IN_PREFIX "xtal" },
                .num_parents = 1,
        },
 };
@@ -701,7 +702,7 @@ static struct clk_regmap axg_pcie_pll_dco = {
        .hw.init = &(struct clk_init_data){
                .name = "pcie_pll_dco",
                .ops = &meson_clk_pll_ops,
-               .parent_names = (const char *[]){ "xtal" },
+               .parent_names = (const char *[]){ IN_PREFIX "xtal" },
                .num_parents = 1,
        },
 };
@@ -803,7 +804,7 @@ static struct clk_regmap axg_pcie_cml_en1 = {
 
 static u32 mux_table_clk81[]   = { 0, 2, 3, 4, 5, 6, 7 };
 static const char * const clk81_parent_names[] = {
-       "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
+       IN_PREFIX "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
        "fclk_div3", "fclk_div5"
 };
 
@@ -852,7 +853,7 @@ static struct clk_regmap axg_clk81 = {
 };
 
 static const char * const axg_sd_emmc_clk0_parent_names[] = {
-       "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
+       IN_PREFIX "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
 
        /*
         * Following these parent clocks, we should also have had mpll2, mpll3
@@ -957,7 +958,7 @@ static struct clk_regmap axg_sd_emmc_c_clk0 = {
 static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,
                                    9, 10, 11, 13, 14, };
 static const char * const gen_clk_parent_names[] = {
-       "xtal", "hifi_pll", "mpll0", "mpll1", "mpll2", "mpll3",
+       IN_PREFIX "xtal", "hifi_pll", "mpll0", "mpll1", "mpll2", "mpll3",
        "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "gp0_pll",
 };
 
@@ -1255,46 +1256,20 @@ static struct clk_regmap *const axg_clk_regmaps[] = {
        &axg_pcie_pll_od,
 };
 
+static const struct meson_eeclkc_data axg_clkc_data = {
+       .regmap_clks = axg_clk_regmaps,
+       .regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
+       .hw_onecell_data = &axg_hw_onecell_data,
+};
+
+
 static const struct of_device_id clkc_match_table[] = {
-       { .compatible = "amlogic,axg-clkc" },
+       { .compatible = "amlogic,axg-clkc", .data = &axg_clkc_data },
        {}
 };
 
-static int axg_clkc_probe(struct platform_device *pdev)
-{
-       struct device *dev = &pdev->dev;
-       struct regmap *map;
-       int ret, i;
-
-       /* Get the hhi system controller node if available */
-       map = syscon_node_to_regmap(of_get_parent(dev->of_node));
-       if (IS_ERR(map)) {
-               dev_err(dev, "failed to get HHI regmap\n");
-               return PTR_ERR(map);
-       }
-
-       /* Populate regmap for the regmap backed clocks */
-       for (i = 0; i < ARRAY_SIZE(axg_clk_regmaps); i++)
-               axg_clk_regmaps[i]->map = map;
-
-       for (i = 0; i < axg_hw_onecell_data.num; i++) {
-               /* array might be sparse */
-               if (!axg_hw_onecell_data.hws[i])
-                       continue;
-
-               ret = devm_clk_hw_register(dev, axg_hw_onecell_data.hws[i]);
-               if (ret) {
-                       dev_err(dev, "Clock registration failed\n");
-                       return ret;
-               }
-       }
-
-       return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
-                                          &axg_hw_onecell_data);
-}
-
 static struct platform_driver axg_driver = {
-       .probe          = axg_clkc_probe,
+       .probe          = meson_eeclkc_probe,
        .driver         = {
                .name   = "axg-clkc",
                .of_match_table = clkc_match_table,