Merge tag 'idmapped-mounts-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git...

[linux-2.6-microblaze.git] / drivers / clk / clk-qoriq.c

diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 70aa521..88898b9 100644 (file)
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
  *
  * clock driver for Freescale QorIQ SoCs.
  */
@@ -564,7 +565,9 @@ static const struct clockgen_chipinfo chipinfo[] = {
                .cmux_to_group = {
                        0, 1, 1, 1, -1
                },
-               .pll_mask = 0x3f,
+               .pll_mask = BIT(PLATFORM_PLL) |
+                           BIT(CGA_PLL1) | BIT(CGA_PLL2) | BIT(CGA_PLL3) |
+                           BIT(CGB_PLL1) | BIT(CGB_PLL2),
                .flags = CG_PLL_8BIT,
        },
        {
@@ -580,7 +583,9 @@ static const struct clockgen_chipinfo chipinfo[] = {
                .cmux_to_group = {
                        0, 1, 1, 1, -1
                },
-               .pll_mask = 0x3f,
+               .pll_mask = BIT(PLATFORM_PLL) |
+                           BIT(CGA_PLL1) | BIT(CGA_PLL2) | BIT(CGA_PLL3) |
+                           BIT(CGB_PLL1) | BIT(CGB_PLL2),
                .flags = CG_PLL_8BIT,
        },
        {
@@ -591,7 +596,8 @@ static const struct clockgen_chipinfo chipinfo[] = {
                .cmux_to_group = {
                        0, -1
                },
-               .pll_mask = 0x03,
+               .pll_mask = BIT(PLATFORM_PLL) |
+                           BIT(CGA_PLL1) | BIT(CGA_PLL2),
        },
        {
                .compat = "fsl,ls1028a-clockgen",
@@ -605,7 +611,8 @@ static const struct clockgen_chipinfo chipinfo[] = {
                .cmux_to_group = {
                        0, 0, 0, 0, -1
                },
-               .pll_mask = 0x07,
+               .pll_mask = BIT(PLATFORM_PLL) |
+                           BIT(CGA_PLL1) | BIT(CGA_PLL2),
                .flags = CG_VER3 | CG_LITTLE_ENDIAN,
        },
        {
@@ -620,7 +627,8 @@ static const struct clockgen_chipinfo chipinfo[] = {
                .cmux_to_group = {
                        0, -1
                },
-               .pll_mask = 0x07,
+               .pll_mask = BIT(PLATFORM_PLL) |
+                           BIT(CGA_PLL1) | BIT(CGA_PLL2),
                .flags = CG_PLL_8BIT,
        },
        {
@@ -635,7 +643,8 @@ static const struct clockgen_chipinfo chipinfo[] = {
                .cmux_to_group = {
                        0, -1
                },
-               .pll_mask = 0x07,
+               .pll_mask = BIT(PLATFORM_PLL) |
+                           BIT(CGA_PLL1) | BIT(CGA_PLL2),
                .flags = CG_PLL_8BIT,
        },
        {
@@ -649,7 +658,8 @@ static const struct clockgen_chipinfo chipinfo[] = {
                .cmux_to_group = {
                        0, 0, -1
                },
-               .pll_mask = 0x07,
+               .pll_mask = BIT(PLATFORM_PLL) |
+                           BIT(CGA_PLL1) | BIT(CGA_PLL2),
                .flags = CG_VER3 | CG_LITTLE_ENDIAN,
        },
        {
@@ -660,7 +670,7 @@ static const struct clockgen_chipinfo chipinfo[] = {
                .cmux_to_group = {
                        0, -1
                },
-               .pll_mask = 0x03,
+               .pll_mask = BIT(PLATFORM_PLL) | BIT(CGA_PLL1),
        },
        {
                .compat = "fsl,ls2080a-clockgen",
@@ -670,7 +680,9 @@ static const struct clockgen_chipinfo chipinfo[] = {
                .cmux_to_group = {
                        0, 0, 1, 1, -1
                },
-               .pll_mask = 0x37,
+               .pll_mask = BIT(PLATFORM_PLL) |
+                           BIT(CGA_PLL1) | BIT(CGA_PLL2) |
+                           BIT(CGB_PLL1) | BIT(CGB_PLL2),
                .flags = CG_VER3 | CG_LITTLE_ENDIAN,
        },
        {
@@ -681,7 +693,9 @@ static const struct clockgen_chipinfo chipinfo[] = {
                .cmux_to_group = {
                        0, 0, 0, 0, 1, 1, 1, 1, -1
                },
-               .pll_mask = 0x37,
+               .pll_mask = BIT(PLATFORM_PLL) |
+                           BIT(CGA_PLL1) | BIT(CGA_PLL2) |
+                           BIT(CGB_PLL1) | BIT(CGB_PLL2),
                .flags = CG_VER3 | CG_LITTLE_ENDIAN,
        },
        {
@@ -694,7 +708,8 @@ static const struct clockgen_chipinfo chipinfo[] = {
                .cmux_to_group = {
                        0, 0, 1, 1, -1
                },
-               .pll_mask = 0x07,
+               .pll_mask = BIT(PLATFORM_PLL) |
+                           BIT(CGA_PLL1) | BIT(CGA_PLL2),
        },
        {
                .compat = "fsl,p3041-clockgen",
@@ -706,7 +721,8 @@ static const struct clockgen_chipinfo chipinfo[] = {
                .cmux_to_group = {
                        0, 0, 1, 1, -1
                },
-               .pll_mask = 0x07,
+               .pll_mask = BIT(PLATFORM_PLL) |
+                           BIT(CGA_PLL1) | BIT(CGA_PLL2),
        },
        {
                .compat = "fsl,p4080-clockgen",
@@ -718,7 +734,9 @@ static const struct clockgen_chipinfo chipinfo[] = {
                .cmux_to_group = {
                        0, 0, 0, 0, 1, 1, 1, 1, -1
                },
-               .pll_mask = 0x1f,
+               .pll_mask = BIT(PLATFORM_PLL) |
+                           BIT(CGA_PLL1) | BIT(CGA_PLL2) |
+                           BIT(CGA_PLL3) | BIT(CGA_PLL4),
        },
        {
                .compat = "fsl,p5020-clockgen",
@@ -730,7 +748,8 @@ static const struct clockgen_chipinfo chipinfo[] = {
                .cmux_to_group = {
                        0, 1, -1
                },
-               .pll_mask = 0x07,
+               .pll_mask = BIT(PLATFORM_PLL) |
+                           BIT(CGA_PLL1) | BIT(CGA_PLL2),
        },
        {
                .compat = "fsl,p5040-clockgen",
@@ -742,7 +761,8 @@ static const struct clockgen_chipinfo chipinfo[] = {
                .cmux_to_group = {
                        0, 0, 1, 1, -1
                },
-               .pll_mask = 0x0f,
+               .pll_mask = BIT(PLATFORM_PLL) |
+                           BIT(CGA_PLL1) | BIT(CGA_PLL2) | BIT(CGA_PLL3),
        },
        {
                .compat = "fsl,t1023-clockgen",
@@ -757,7 +777,7 @@ static const struct clockgen_chipinfo chipinfo[] = {
                .cmux_to_group = {
                        0, 0, -1
                },
-               .pll_mask = 0x03,
+               .pll_mask = BIT(PLATFORM_PLL) | BIT(CGA_PLL1),
                .flags = CG_PLL_8BIT,
        },
        {
@@ -770,7 +790,8 @@ static const struct clockgen_chipinfo chipinfo[] = {
                .cmux_to_group = {
                        0, 0, 0, 0, -1
                },
-               .pll_mask = 0x07,
+               .pll_mask = BIT(PLATFORM_PLL) |
+                           BIT(CGA_PLL1) | BIT(CGA_PLL2),
                .flags = CG_PLL_8BIT,
        },
        {
@@ -786,7 +807,8 @@ static const struct clockgen_chipinfo chipinfo[] = {
                .cmux_to_group = {
                        0, -1
                },
-               .pll_mask = 0x07,
+               .pll_mask = BIT(PLATFORM_PLL) |
+                           BIT(CGA_PLL1) | BIT(CGA_PLL2),
                .flags = CG_PLL_8BIT,
        },
        {
@@ -802,7 +824,9 @@ static const struct clockgen_chipinfo chipinfo[] = {
                .cmux_to_group = {
                        0, 0, 1, -1
                },
-               .pll_mask = 0x3f,
+               .pll_mask = BIT(PLATFORM_PLL) |
+                           BIT(CGA_PLL1) | BIT(CGA_PLL2) | BIT(CGA_PLL3) |
+                           BIT(CGB_PLL1) | BIT(CGB_PLL2),
                .flags = CG_PLL_8BIT,
        },
        {},