cache: Add L2 cache management for Andes AX45MP RISC-V core

[linux-2.6-microblaze.git] / drivers / Makefile

diff --git a/drivers/Makefile b/drivers/Makefile
index 7241d80..23eb201 100644 (file)
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -11,6 +11,7 @@ ifdef building_out_of_srctree
 MAKEFLAGS += --include-dir=$(srctree)
 endif
 
+obj-y                          += cache/
 obj-y                          += irqchip/
 obj-y                          += bus/