Merge tag 'x86_seves_for_v5.10' of git://git.kernel.org/pub/scm/linux/kernel/git...

[linux-2.6-microblaze.git] / arch / x86 / kernel / cpu / common.c

diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index c511589..35ad848 100644 (file)
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1876,6 +1876,8 @@ static inline void tss_setup_ist(struct tss_struct *tss)
        tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI);
        tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB);
        tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE);
+       /* Only mapped when SEV-ES is active */
+       tss->x86_tss.ist[IST_INDEX_VC] = __this_cpu_ist_top_va(VC);
 }
 
 #else /* CONFIG_X86_64 */
@@ -1907,6 +1909,29 @@ static inline void tss_setup_io_bitmap(struct tss_struct *tss)
 #endif
 }
 
+/*
+ * Setup everything needed to handle exceptions from the IDT, including the IST
+ * exceptions which use paranoid_entry().
+ */
+void cpu_init_exception_handling(void)
+{
+       struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
+       int cpu = raw_smp_processor_id();
+
+       /* paranoid_entry() gets the CPU number from the GDT */
+       setup_getcpu(cpu);
+
+       /* IST vectors need TSS to be set up. */
+       tss_setup_ist(tss);
+       tss_setup_io_bitmap(tss);
+       set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
+
+       load_TR_desc();
+
+       /* Finally load the IDT */
+       load_current_idt();
+}
+
 /*
  * cpu_init() initializes state that is per-CPU. Some data is already
  * initialized (naturally) in the bootstrap process, such as the GDT