x86, olpc: EC SCI wakeup mask functionality

[linux-2.6-microblaze.git] / arch / x86 / include / asm / olpc.h

diff --git a/arch/x86/include/asm/olpc.h b/arch/x86/include/asm/olpc.h
index 10ea595..0e56d01 100644 (file)
--- a/arch/x86/include/asm/olpc.h
+++ b/arch/x86/include/asm/olpc.h
@@ -13,6 +13,7 @@ struct olpc_platform_t {
 
 #define OLPC_F_PRESENT         0x01
 #define OLPC_F_DCON            0x02
+#define OLPC_F_EC_WIDE_SCI     0x04
 
 #ifdef CONFIG_OLPC
 
@@ -62,6 +63,13 @@ static inline int olpc_board_at_least(uint32_t rev)
        return olpc_platform_info.boardrev >= rev;
 }
 
+extern void olpc_ec_wakeup_set(u16 value);
+extern void olpc_ec_wakeup_clear(u16 value);
+extern bool olpc_ec_wakeup_available(void);
+
+extern int olpc_ec_mask_write(u16 bits);
+extern int olpc_ec_sci_query(u16 *sci_value);
+
 #else
 
 static inline int machine_is_olpc(void)
@@ -74,6 +82,14 @@ static inline int olpc_has_dcon(void)
        return 0;
 }
 
+static inline void olpc_ec_wakeup_set(u16 value) { }
+static inline void olpc_ec_wakeup_clear(u16 value) { }
+
+static inline bool olpc_ec_wakeup_available(void)
+{
+       return false;
+}
+
 #endif
 
 #ifdef CONFIG_OLPC_XO1_PM
@@ -89,17 +105,18 @@ extern int pci_olpc_init(void);
 extern int olpc_ec_cmd(unsigned char cmd, unsigned char *inbuf, size_t inlen,
                unsigned char *outbuf, size_t outlen);
 
-extern int olpc_ec_mask_set(uint8_t bits);
-extern int olpc_ec_mask_unset(uint8_t bits);
-
 /* EC commands */
 
 #define EC_FIRMWARE_REV                        0x08
+#define EC_WRITE_SCI_MASK              0x1b
 #define EC_WAKE_UP_WLAN                        0x24
 #define EC_WLAN_LEAVE_RESET            0x25
 #define EC_SET_SCI_INHIBIT             0x32
 #define EC_SET_SCI_INHIBIT_RELEASE     0x34
 #define EC_WLAN_ENTER_RESET            0x35
+#define EC_WRITE_EXT_SCI_MASK          0x38
+#define EC_SCI_QUERY                   0x84
+#define EC_EXT_SCI_QUERY               0x85
 
 /* SCI source values */
 
@@ -108,10 +125,12 @@ extern int olpc_ec_mask_unset(uint8_t bits);
 #define EC_SCI_SRC_BATTERY     0x02
 #define EC_SCI_SRC_BATSOC      0x04
 #define EC_SCI_SRC_BATERR      0x08
-#define EC_SCI_SRC_EBOOK       0x10
-#define EC_SCI_SRC_WLAN                0x20
+#define EC_SCI_SRC_EBOOK       0x10    /* XO-1 only */
+#define EC_SCI_SRC_WLAN                0x20    /* XO-1 only */
 #define EC_SCI_SRC_ACPWR       0x40
-#define EC_SCI_SRC_ALL         0x7F
+#define EC_SCI_SRC_BATCRIT     0x80
+#define EC_SCI_SRC_GPWAKE      0x100   /* XO-1.5 only */
+#define EC_SCI_SRC_ALL         0x1FF
 
 /* GPIO assignments */