perf/amd/uncore: Set all slices and threads to restore perf stat -a behaviour

[linux-2.6-microblaze.git] / arch / x86 / events / amd / uncore.c

diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index 76400c0..e7e61c8 100644 (file)
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -181,28 +181,16 @@ static void amd_uncore_del(struct perf_event *event, int flags)
 }
 
 /*
- * Convert logical CPU number to L3 PMC Config ThreadMask format
+ * Return a full thread and slice mask until per-CPU is
+ * properly supported.
  */
-static u64 l3_thread_slice_mask(int cpu)
+static u64 l3_thread_slice_mask(void)
 {
-       u64 thread_mask, core = topology_core_id(cpu);
-       unsigned int shift, thread = 0;
+       if (boot_cpu_data.x86 <= 0x18)
+               return AMD64_L3_SLICE_MASK | AMD64_L3_THREAD_MASK;
 
-       if (topology_smt_supported() && !topology_is_primary_thread(cpu))
-               thread = 1;
-
-       if (boot_cpu_data.x86 <= 0x18) {
-               shift = AMD64_L3_THREAD_SHIFT + 2 * (core % 4) + thread;
-               thread_mask = BIT_ULL(shift);
-
-               return AMD64_L3_SLICE_MASK | thread_mask;
-       }
-
-       core = (core << AMD64_L3_COREID_SHIFT) & AMD64_L3_COREID_MASK;
-       shift = AMD64_L3_THREAD_SHIFT + thread;
-       thread_mask = BIT_ULL(shift);
-
-       return AMD64_L3_EN_ALL_SLICES | core | thread_mask;
+       return AMD64_L3_EN_ALL_SLICES | AMD64_L3_EN_ALL_CORES |
+              AMD64_L3_F19H_THREAD_MASK;
 }
 
 static int amd_uncore_event_init(struct perf_event *event)
@@ -232,7 +220,7 @@ static int amd_uncore_event_init(struct perf_event *event)
         * For other events, the two fields do not affect the count.
         */
        if (l3_mask && is_llc_event(event))
-               hwc->config |= l3_thread_slice_mask(event->cpu);
+               hwc->config |= l3_thread_slice_mask();
 
        uncore = event_to_amd_uncore(event);
        if (!uncore)