Merge tag 'perf-tools-for-v5.17-2022-01-22' of git://git.kernel.org/pub/scm/linux...

[linux-2.6-microblaze.git] / arch / riscv / kernel / head.S

diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 52c5ff9..2363b43 100644 (file)
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -11,6 +11,7 @@
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include <asm/csr.h>
+#include <asm/cpu_ops_sbi.h>
 #include <asm/hwcap.h>
 #include <asm/image.h>
 #include "efi-header.S"
@@ -20,10 +21,20 @@
        REG_L t0, _xip_fixup
        add \reg, \reg, t0
 .endm
+.macro XIP_FIXUP_FLASH_OFFSET reg
+       la t1, __data_loc
+       li t0, XIP_OFFSET_MASK
+       and t1, t1, t0
+       li t1, XIP_OFFSET
+       sub t0, t0, t1
+       sub \reg, \reg, t0
+.endm
 _xip_fixup: .dword CONFIG_PHYS_RAM_BASE - CONFIG_XIP_PHYS_ADDR - XIP_OFFSET
 #else
 .macro XIP_FIXUP_OFFSET reg
 .endm
+.macro XIP_FIXUP_FLASH_OFFSET reg
+.endm
 #endif /* CONFIG_XIP_KERNEL */
 
 __HEAD
@@ -95,7 +106,8 @@ relocate:
 
        /* Compute satp for kernel page tables, but don't load it yet */
        srl a2, a0, PAGE_SHIFT
-       li a1, SATP_MODE
+       la a1, satp_mode
+       REG_L a1, 0(a1)
        or a2, a2, a1
 
        /*
@@ -125,7 +137,7 @@ relocate:
        /*
         * Switch to kernel page tables.  A full fence is necessary in order to
         * avoid using the trampoline translations, which are only correct for
-        * the first superpage.  Fetching the fence is guarnteed to work
+        * the first superpage.  Fetching the fence is guaranteed to work
         * because that first superpage is translated the same way.
         */
        csrw CSR_SATP, a2
@@ -157,18 +169,17 @@ secondary_start_sbi:
        la a3, .Lsecondary_park
        csrw CSR_TVEC, a3
 
-       slli a3, a0, LGREG
-       la a4, __cpu_up_stack_pointer
-       XIP_FIXUP_OFFSET a4
-       la a5, __cpu_up_task_pointer
-       XIP_FIXUP_OFFSET a5
-       add a4, a3, a4
-       add a5, a3, a5
-       REG_L sp, (a4)
-       REG_L tp, (a5)
-
-       .global secondary_start_common
-secondary_start_common:
+       /* a0 contains the hartid & a1 contains boot data */
+       li a2, SBI_HART_BOOT_TASK_PTR_OFFSET
+       XIP_FIXUP_OFFSET a2
+       add a2, a2, a1
+       REG_L tp, (a2)
+       li a3, SBI_HART_BOOT_STACK_PTR_OFFSET
+       XIP_FIXUP_OFFSET a3
+       add a3, a3, a1
+       REG_L sp, (a3)
+
+.Lsecondary_start_common:
 
 #ifdef CONFIG_MMU
        /* Enable virtual memory and relocate to virtual address */
@@ -248,13 +259,13 @@ pmp_done:
        li t0, SR_FS
        csrc CSR_STATUS, t0
 
-#ifdef CONFIG_SMP
+#ifdef CONFIG_RISCV_BOOT_SPINWAIT
        li t0, CONFIG_NR_CPUS
        blt a0, t0, .Lgood_cores
        tail .Lsecondary_park
 .Lgood_cores:
-#endif
 
+       /* The lottery system is only required for spinwait booting method */
 #ifndef CONFIG_XIP_KERNEL
        /* Pick one hart to run the main boot sequence */
        la a3, hart_lottery
@@ -267,11 +278,16 @@ pmp_done:
        la a3, hart_lottery
        mv a2, a3
        XIP_FIXUP_OFFSET a2
+       XIP_FIXUP_FLASH_OFFSET a3
        lw t1, (a3)
        amoswap.w t0, t1, (a2)
        /* first time here if hart_lottery in RAM is not set */
        beq t0, t1, .Lsecondary_start
 
+#endif /* CONFIG_XIP */
+#endif /* CONFIG_RISCV_BOOT_SPINWAIT */
+
+#ifdef CONFIG_XIP_KERNEL
        la sp, _end + THREAD_SIZE
        XIP_FIXUP_OFFSET sp
        mv s0, a0
@@ -305,6 +321,7 @@ clear_bss_done:
        XIP_FIXUP_OFFSET sp
 #ifdef CONFIG_BUILTIN_DTB
        la a0, __dtb_start
+       XIP_FIXUP_OFFSET a0
 #else
        mv a0, s1
 #endif /* CONFIG_BUILTIN_DTB */
@@ -318,7 +335,6 @@ clear_bss_done:
        call setup_trap_vector
        /* Restore C environment */
        la tp, init_task
-       sw zero, TASK_TI_CPU(tp)
        la sp, init_thread_union + THREAD_SIZE
 
 #ifdef CONFIG_KASAN
@@ -328,16 +344,16 @@ clear_bss_done:
        call soc_early_init
        tail start_kernel
 
+#if CONFIG_RISCV_BOOT_SPINWAIT
 .Lsecondary_start:
-#ifdef CONFIG_SMP
        /* Set trap vector to spin forever to help debug */
        la a3, .Lsecondary_park
        csrw CSR_TVEC, a3
 
        slli a3, a0, LGREG
-       la a1, __cpu_up_stack_pointer
+       la a1, __cpu_spinwait_stack_pointer
        XIP_FIXUP_OFFSET a1
-       la a2, __cpu_up_task_pointer
+       la a2, __cpu_spinwait_task_pointer
        XIP_FIXUP_OFFSET a2
        add a1, a3, a1
        add a2, a3, a2
@@ -354,8 +370,8 @@ clear_bss_done:
        beqz tp, .Lwait_for_cpu_up
        fence
 
-       tail secondary_start_common
-#endif
+       tail .Lsecondary_start_common
+#endif /* CONFIG_RISCV_BOOT_SPINWAIT */
 
 END(_start_kernel)
 
@@ -437,7 +453,3 @@ ENTRY(reset_regs)
        ret
 END(reset_regs)
 #endif /* CONFIG_RISCV_M_MODE */
-
-__PAGE_ALIGNED_BSS
-       /* Empty zero page */
-       .balign PAGE_SIZE