riscv: Unaligned load/store handling for M_MODE

[linux-2.6-microblaze.git] / arch / riscv / kernel / Makefile

diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
index c121cc4..1bad93f 100644 (file)
--- a/arch/riscv/kernel/Makefile
+++ b/arch/riscv/kernel/Makefile
@@ -30,7 +30,7 @@ obj-y += cacheinfo.o
 obj-y  += patch.o
 obj-$(CONFIG_MMU) += vdso.o vdso/
 
-obj-$(CONFIG_RISCV_M_MODE)     += clint.o
+obj-$(CONFIG_RISCV_M_MODE)     += clint.o traps_misaligned.o
 obj-$(CONFIG_FPU)              += fpu.o
 obj-$(CONFIG_SMP)              += smpboot.o
 obj-$(CONFIG_SMP)              += smp.o