riscv/barrier: Consolidate fence definitions

[linux-2.6-microblaze.git] / arch / riscv / include / asm / io.h

diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
index 42497d4..1c5c641 100644 (file)
--- a/arch/riscv/include/asm/io.h
+++ b/arch/riscv/include/asm/io.h
@@ -47,10 +47,10 @@
  * sufficient to ensure this works sanely on controllers that support I/O
  * writes.
  */
-#define __io_pbr()     __asm__ __volatile__ ("fence io,i"  : : : "memory");
-#define __io_par(v)    __asm__ __volatile__ ("fence i,ior" : : : "memory");
-#define __io_pbw()     __asm__ __volatile__ ("fence iow,o" : : : "memory");
-#define __io_paw()     __asm__ __volatile__ ("fence o,io"  : : : "memory");
+#define __io_pbr()     RISCV_FENCE(io, i)
+#define __io_par(v)    RISCV_FENCE(i, ior)
+#define __io_pbw()     RISCV_FENCE(iow, o)
+#define __io_paw()     RISCV_FENCE(o, io)
 
 /*
  * Accesses from a single hart to a single I/O address must be ordered.  This