RISC-V: fix sifive and thead section mismatches in errata

[linux-2.6-microblaze.git] / arch / riscv / errata / sifive / errata.c

diff --git a/arch/riscv/errata/sifive/errata.c b/arch/riscv/errata/sifive/errata.c
index 8d8301d..3d9a32d 100644 (file)
--- a/arch/riscv/errata/sifive/errata.c
+++ b/arch/riscv/errata/sifive/errata.c
@@ -82,11 +82,9 @@ static void __init_or_module warn_miss_errata(u32 miss_errata)
        pr_warn("----------------------------------------------------------------\n");
 }
 
-void __init_or_module sifive_errata_patch_func(struct alt_entry *begin,
-                                              struct alt_entry *end,
-                                              unsigned long archid,
-                                              unsigned long impid,
-                                              unsigned int stage)
+void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
+                             unsigned long archid, unsigned long impid,
+                             unsigned int stage)
 {
        struct alt_entry *alt;
        u32 cpu_req_errata;