powerpc/perf: Adds support for programming of Thresholding in P10

[linux-2.6-microblaze.git] / arch / powerpc / perf / power6-pmu.c

diff --git a/arch/powerpc/perf/power6-pmu.c b/arch/powerpc/perf/power6-pmu.c
index 1899744..69ef382 100644 (file)
--- a/arch/powerpc/perf/power6-pmu.c
+++ b/arch/powerpc/perf/power6-pmu.c
@@ -173,7 +173,8 @@ static int power6_marked_instr_event(u64 event)
  * Assign PMC numbers and compute MMCR1 value for a set of events
  */
 static int p6_compute_mmcr(u64 event[], int n_ev,
-                          unsigned int hwc[], struct mmcr_regs *mmcr, struct perf_event *pevents[])
+                          unsigned int hwc[], struct mmcr_regs *mmcr, struct perf_event *pevents[],
+                          u32 flags __maybe_unused)
 {
        unsigned long mmcr1 = 0;
        unsigned long mmcra = MMCRA_SDAR_DCACHE_MISS | MMCRA_SDAR_ERAT_MISS;
@@ -266,7 +267,7 @@ static int p6_compute_mmcr(u64 event[], int n_ev,
  *     32-34   select field: nest (subunit) event selector
  */
 static int p6_get_constraint(u64 event, unsigned long *maskp,
-                            unsigned long *valp)
+                            unsigned long *valp, u64 event_config1 __maybe_unused)
 {
        int pmc, byte, sh, subunit;
        unsigned long mask = 0, value = 0;