Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
[linux-2.6-microblaze.git] / arch / mips / loongson64 / env.c
index d11bc34..134cb8e 100644 (file)
@@ -126,28 +126,6 @@ void __init prom_init_env(void)
                loongson_sysconf.cores_per_node - 1) /
                loongson_sysconf.cores_per_node;
 
-       if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64C) {
-               switch (read_c0_prid() & PRID_REV_MASK) {
-               case PRID_REV_LOONGSON3A_R1:
-               case PRID_REV_LOONGSON3A_R2_0:
-               case PRID_REV_LOONGSON3A_R2_1:
-               case PRID_REV_LOONGSON3A_R3_0:
-               case PRID_REV_LOONGSON3A_R3_1:
-                       loongson_fdt_blob = __dtb_loongson3_4core_rs780e_begin;
-                       break;
-               case PRID_REV_LOONGSON3B_R1:
-               case PRID_REV_LOONGSON3B_R2:
-                       loongson_fdt_blob = __dtb_loongson3_8core_rs780e_begin;
-                       break;
-               default:
-                       break;
-               }
-       }
-
-
-       if (!loongson_fdt_blob)
-               pr_err("Failed to determine built-in Loongson64 dtb\n");
-
        loongson_sysconf.pci_mem_start_addr = eirq_source->pci_mem_start_addr;
        loongson_sysconf.pci_mem_end_addr = eirq_source->pci_mem_end_addr;
        loongson_sysconf.pci_io_base = eirq_source->pci_io_start_addr;
@@ -189,13 +167,57 @@ void __init prom_init_env(void)
        vendor = id & 0xffff;
        device = (id >> 16) & 0xffff;
 
-       if (vendor == PCI_VENDOR_ID_LOONGSON && device == 0x7a00) {
+       switch (vendor) {
+       case PCI_VENDOR_ID_LOONGSON:
                pr_info("The bridge chip is LS7A\n");
                loongson_sysconf.bridgetype = LS7A;
                loongson_sysconf.early_config = ls7a_early_config;
-       } else {
+               break;
+       case PCI_VENDOR_ID_AMD:
+       case PCI_VENDOR_ID_ATI:
                pr_info("The bridge chip is RS780E or SR5690\n");
                loongson_sysconf.bridgetype = RS780E;
                loongson_sysconf.early_config = rs780e_early_config;
+               break;
+       default:
+               pr_info("The bridge chip is VIRTUAL\n");
+               loongson_sysconf.bridgetype = VIRTUAL;
+               loongson_sysconf.early_config = virtual_early_config;
+               loongson_fdt_blob = __dtb_loongson64v_4core_virtio_begin;
+               break;
        }
+
+       if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64C) {
+               switch (read_c0_prid() & PRID_REV_MASK) {
+               case PRID_REV_LOONGSON3A_R1:
+               case PRID_REV_LOONGSON3A_R2_0:
+               case PRID_REV_LOONGSON3A_R2_1:
+               case PRID_REV_LOONGSON3A_R3_0:
+               case PRID_REV_LOONGSON3A_R3_1:
+                       switch (loongson_sysconf.bridgetype) {
+                       case LS7A:
+                               loongson_fdt_blob = __dtb_loongson64c_4core_ls7a_begin;
+                               break;
+                       case RS780E:
+                               loongson_fdt_blob = __dtb_loongson64c_4core_rs780e_begin;
+                               break;
+                       default:
+                               break;
+                       }
+                       break;
+               case PRID_REV_LOONGSON3B_R1:
+               case PRID_REV_LOONGSON3B_R2:
+                       if (loongson_sysconf.bridgetype == RS780E)
+                               loongson_fdt_blob = __dtb_loongson64c_8core_rs780e_begin;
+                       break;
+               default:
+                       break;
+               }
+       } else if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64G) {
+               if (loongson_sysconf.bridgetype == LS7A)
+                       loongson_fdt_blob = __dtb_loongson64g_4core_ls7a_begin;
+       }
+
+       if (!loongson_fdt_blob)
+               pr_err("Failed to determine built-in Loongson64 dtb\n");
 }