MIPS: Drop Loongson _CACHE_* definitions

[linux-2.6-microblaze.git] / arch / mips / include / asm / pgtable-bits.h

diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index f88a48c..409ae01 100644 (file)
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -52,6 +52,7 @@ enum pgtable_bits {
        _PAGE_WRITE_SHIFT,
        _PAGE_ACCESSED_SHIFT,
        _PAGE_MODIFIED_SHIFT,
+       _PAGE_SPECIAL_SHIFT,
 };
 
 /*
@@ -78,9 +79,10 @@ enum pgtable_bits {
        _PAGE_WRITE_SHIFT,
        _PAGE_ACCESSED_SHIFT,
        _PAGE_MODIFIED_SHIFT,
+       _PAGE_SPECIAL_SHIFT,
 };
 
-#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+#elif defined(CONFIG_CPU_R3K_TLB)
 
 /* Page table bits used for r3k systems */
 enum pgtable_bits {
@@ -90,6 +92,7 @@ enum pgtable_bits {
        _PAGE_WRITE_SHIFT,
        _PAGE_ACCESSED_SHIFT,
        _PAGE_MODIFIED_SHIFT,
+       _PAGE_SPECIAL_SHIFT,
 
        /* Used by TLB hardware (placed in EntryLo) */
        _PAGE_GLOBAL_SHIFT = 8,
@@ -110,9 +113,10 @@ enum pgtable_bits {
        _PAGE_WRITE_SHIFT,
        _PAGE_ACCESSED_SHIFT,
        _PAGE_MODIFIED_SHIFT,
-#if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
+#if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
        _PAGE_HUGE_SHIFT,
 #endif
+       _PAGE_SPECIAL_SHIFT,
 
        /* Used by TLB hardware (placed in EntryLo*) */
 #if defined(CONFIG_CPU_HAS_RIXI)
@@ -132,9 +136,10 @@ enum pgtable_bits {
 #define _PAGE_WRITE            (1 << _PAGE_WRITE_SHIFT)
 #define _PAGE_ACCESSED         (1 << _PAGE_ACCESSED_SHIFT)
 #define _PAGE_MODIFIED         (1 << _PAGE_MODIFIED_SHIFT)
-#if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
+#if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
 # define _PAGE_HUGE            (1 << _PAGE_HUGE_SHIFT)
 #endif
+#define _PAGE_SPECIAL          (1 << _PAGE_SPECIAL_SHIFT)
 
 /* Used by TLB hardware (placed in EntryLo*) */
 #if defined(CONFIG_XPA)
@@ -146,7 +151,7 @@ enum pgtable_bits {
 #define _PAGE_GLOBAL           (1 << _PAGE_GLOBAL_SHIFT)
 #define _PAGE_VALID            (1 << _PAGE_VALID_SHIFT)
 #define _PAGE_DIRTY            (1 << _PAGE_DIRTY_SHIFT)
-#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+#if defined(CONFIG_CPU_R3K_TLB)
 # define _CACHE_UNCACHED       (1 << _CACHE_UNCACHED_SHIFT)
 # define _CACHE_MASK           _CACHE_UNCACHED
 # define _PFN_SHIFT            PAGE_SHIFT
@@ -204,7 +209,7 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
 /*
  * Cache attributes
  */
-#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+#if defined(CONFIG_CPU_R3K_TLB)
 
 #define _CACHE_CACHABLE_NONCOHERENT 0
 #define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED
@@ -216,13 +221,6 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
 
 #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
 
-#elif defined(CONFIG_CPU_LOONGSON3)
-
-/* Using COHERENT flag for NONCOHERENT doesn't hurt. */
-
-#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)  /* LOONGSON       */
-#define _CACHE_CACHABLE_COHERENT    (3<<_CACHE_SHIFT)  /* LOONGSON-3     */
-
 #elif defined(CONFIG_MACH_INGENIC)
 
 /* Ingenic uses the WA bit to achieve write-combine memory writes */