MIPS: Convert R4600_V1_HIT_CACHEOP into a config option

[linux-2.6-microblaze.git] / arch / mips / include / asm / mach-ip22 / war.h

diff --git a/arch/mips/include/asm/mach-ip22/war.h b/arch/mips/include/asm/mach-ip22/war.h
index 3424c1e..9154c54 100644 (file)
--- a/arch/mips/include/asm/mach-ip22/war.h
+++ b/arch/mips/include/asm/mach-ip22/war.h
@@ -12,7 +12,6 @@
  * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors.
  */
 
-#define R4600_V1_HIT_CACHEOP_WAR       1
 #define R4600_V2_HIT_CACHEOP_WAR       1
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0