mips: Add CP0 Write Merge config support

[linux-2.6-microblaze.git] / arch / mips / include / asm / cpu.h

diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 4b84fd1..104a509 100644 (file)
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -422,7 +422,9 @@ enum cpu_type_enum {
 #define MIPS_CPU_MT_PER_TC_PERF_COUNTERS \
                                BIT_ULL(56)     /* CPU has perf counters implemented per TC (MIPSMT ASE) */
 #define MIPS_CPU_MMID          BIT_ULL(57)     /* CPU supports MemoryMapIDs */
-#define MIPS_CPU_MAC_2008_ONLY BIT_ULL(58)     /* CPU Only support MAC2008 Fused multiply-add instruction */
+#define MIPS_CPU_MM_SYSAD      BIT_ULL(58)     /* CPU supports write-through SysAD Valid merge */
+#define MIPS_CPU_MM_FULL       BIT_ULL(59)     /* CPU supports write-through full merge */
+#define MIPS_CPU_MAC_2008_ONLY BIT_ULL(60)     /* CPU Only support MAC2008 Fused multiply-add instruction */
 
 /*
  * CPU ASE encodings