config MIPS_GENERIC
bool
+config MACH_GENERIC_CORE
+ bool
+
config MACH_INGENIC
bool
select SYS_SUPPORTS_32BIT_KERNEL
select DMA_NONCOHERENT
select HAVE_PCI
select IRQ_MIPS_CPU
+ select MACH_GENERIC_CORE
select MIPS_AUTO_PFN_OFFSET
select MIPS_CPU_SCACHE
select MIPS_GIC
bool "Ingenic SoC based machines"
select MIPS_GENERIC
select MACH_INGENIC
+ select MACH_GENERIC_CORE
select SYS_SUPPORTS_ZBOOT_UART16550
select CPU_SUPPORTS_CPUFREQ
select MIPS_EXTERNAL_TIMER
Microchip PIC32 is a family of general-purpose 32 bit MIPS core
microcontrollers.
+config MACH_EYEQ5
+ bool "Mobileye EyeQ5 SoC"
+ select MACH_GENERIC_CORE
+ select ARM_AMBA
+ select PHYSICAL_START_BOOL
+ select ARCH_SPARSEMEM_DEFAULT if 64BIT
+ select BOOT_RAW
+ select BUILTIN_DTB
+ select CEVT_R4K
+ select CLKSRC_MIPS_GIC
+ select COMMON_CLK
+ select CPU_MIPSR2_IRQ_EI
+ select CPU_MIPSR2_IRQ_VI
+ select CSRC_R4K
+ select DMA_NONCOHERENT
+ select HAVE_PCI
+ select IRQ_MIPS_CPU
+ select MIPS_AUTO_PFN_OFFSET
+ select MIPS_CPU_SCACHE
+ select MIPS_GIC
+ select MIPS_L1_CACHE_SHIFT_7
+ select PCI_DRIVERS_GENERIC
+ select SMP_UP if SMP
+ select SWAP_IO_SPACE
+ select SYS_HAS_CPU_MIPS64_R6
+ select SYS_SUPPORTS_64BIT_KERNEL
+ select SYS_SUPPORTS_HIGHMEM
+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ select SYS_SUPPORTS_MIPS_CPS
+ select SYS_SUPPORTS_RELOCATABLE
+ select SYS_SUPPORTS_ZBOOT
+ select UHI_BOOT
+ select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
+ select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
+ select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
+ select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
+ select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
+ select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
+ select USE_OF
+ help
+ Select this to build a kernel supporting EyeQ5 SoC from Mobileye.
+
+ bool
+
+config FIT_IMAGE_FDT_EPM5
+ bool "Include FDT for Mobileye EyeQ5 development platforms"
+ depends on MACH_EYEQ5
+ default n
+ help
+ Enable this to include the FDT for the EyeQ5 development platforms
+ from Mobileye in the FIT kernel image.
+ This requires u-boot on the platform.
+
config MACH_NINTENDO64
bool "Nintendo 64 console"
select CEVT_R4K
config MACH_REALTEK_RTL
bool "Realtek RTL838x/RTL839x based machines"
select MIPS_GENERIC
+ select MACH_GENERIC_CORE
select DMA_NONCOHERENT
select IRQ_MIPS_CPU
select CSRC_R4K
3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
Loongson-2E/2F is not covered here and will be removed in future.
-config LOONGSON3_ENHANCEMENT
- bool "New Loongson-3 CPU Enhancements"
- default n
- depends on CPU_LOONGSON64
- help
- New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
- R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
- FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
- Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
- Fast TLB refill support, etc.
-
- This option enable those enhancements which are not probed at run
- time. If you want a generic kernel to run on all Loongson 3 machines,
- please say 'N' here. If you want a high-performance kernel to run on
- new Loongson-3 machines only, please say 'Y' here.
-
-config CPU_LOONGSON3_WORKAROUNDS
- bool "Loongson-3 LLSC Workarounds"
- default y if SMP
- depends on CPU_LOONGSON64
- help
- Loongson-3 processors have the llsc issues which require workarounds.
- Without workarounds the system may hang unexpectedly.
-
- Say Y, unless you know what you are doing.
-
-config CPU_LOONGSON3_CPUCFG_EMULATION
- bool "Emulate the CPUCFG instruction on older Loongson cores"
- default y
- depends on CPU_LOONGSON64
- help
- Loongson-3A R4 and newer have the CPUCFG instruction available for
- userland to query CPU capabilities, much like CPUID on x86. This
- option provides emulation of the instruction on older Loongson
- cores, back to Loongson-3A1000.
-
- If unsure, please say Y.
-
config CPU_LOONGSON2E
bool "Loongson 2E"
depends on SYS_HAS_CPU_LOONGSON2E
endchoice
+config LOONGSON3_ENHANCEMENT
+ bool "New Loongson-3 CPU Enhancements"
+ default n
+ depends on CPU_LOONGSON64
+ help
+ New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
+ R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
+ FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
+ Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
+ Fast TLB refill support, etc.
+
+ This option enable those enhancements which are not probed at run
+ time. If you want a generic kernel to run on all Loongson 3 machines,
+ please say 'N' here. If you want a high-performance kernel to run on
+ new Loongson-3 machines only, please say 'Y' here.
+
+config CPU_LOONGSON3_WORKAROUNDS
+ bool "Loongson-3 LLSC Workarounds"
+ default y if SMP
+ depends on CPU_LOONGSON64
+ help
+ Loongson-3 processors have the llsc issues which require workarounds.
+ Without workarounds the system may hang unexpectedly.
+
+ Say Y, unless you know what you are doing.
+
+config CPU_LOONGSON3_CPUCFG_EMULATION
+ bool "Emulate the CPUCFG instruction on older Loongson cores"
+ default y
+ depends on CPU_LOONGSON64
+ help
+ Loongson-3A R4 and newer have the CPUCFG instruction available for
+ userland to query CPU capabilities, much like CPUID on x86. This
+ option provides emulation of the instruction on older Loongson
+ cores, back to Loongson-3A1000.
+
+ If unsure, please say Y.
+
config CPU_MIPS32_3_5_FEATURES
bool "MIPS32 Release 3.5 Features"
depends on SYS_HAS_CPU_MIPS32_R3_5
config MIPS_MT_SMP
bool "MIPS MT SMP support (1 TC on each available VPE)"
default y
- depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
+ depends on TARGET_ISA_REV > 0 && TARGET_ISA_REV < 6
+ depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MICROMIPS
select CPU_MIPSR2_IRQ_VI
select CPU_MIPSR2_IRQ_EI
select SYNC_R4K
projects / linux-2.6-microblaze.git / blobdiff