Merge branches 'for-next/sysreg', 'for-next/sme', 'for-next/kselftest', 'for-next...

[linux-2.6-microblaze.git] / arch / arm64 / include / asm / sysreg.h

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 1312fb4..043ecc3 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -216,101 +216,22 @@
 #define SYS_PAR_EL1_FST                        GENMASK(6, 1)
 
 /*** Statistical Profiling Extension ***/
-/* ID registers */
-#define SYS_PMSIDR_EL1                 sys_reg(3, 0, 9, 9, 7)
-#define SYS_PMSIDR_EL1_FE_SHIFT                0
-#define SYS_PMSIDR_EL1_FT_SHIFT                1
-#define SYS_PMSIDR_EL1_FL_SHIFT                2
-#define SYS_PMSIDR_EL1_ARCHINST_SHIFT  3
-#define SYS_PMSIDR_EL1_LDS_SHIFT       4
-#define SYS_PMSIDR_EL1_ERND_SHIFT      5
-#define SYS_PMSIDR_EL1_INTERVAL_SHIFT  8
-#define SYS_PMSIDR_EL1_INTERVAL_MASK   0xfUL
-#define SYS_PMSIDR_EL1_MAXSIZE_SHIFT   12
-#define SYS_PMSIDR_EL1_MAXSIZE_MASK    0xfUL
-#define SYS_PMSIDR_EL1_COUNTSIZE_SHIFT 16
-#define SYS_PMSIDR_EL1_COUNTSIZE_MASK  0xfUL
-
-#define SYS_PMBIDR_EL1                 sys_reg(3, 0, 9, 10, 7)
-#define SYS_PMBIDR_EL1_ALIGN_SHIFT     0
-#define SYS_PMBIDR_EL1_ALIGN_MASK      0xfU
-#define SYS_PMBIDR_EL1_P_SHIFT         4
-#define SYS_PMBIDR_EL1_F_SHIFT         5
-
-/* Sampling controls */
-#define SYS_PMSCR_EL1                  sys_reg(3, 0, 9, 9, 0)
-#define SYS_PMSCR_EL1_E0SPE_SHIFT      0
-#define SYS_PMSCR_EL1_E1SPE_SHIFT      1
-#define SYS_PMSCR_EL1_CX_SHIFT         3
-#define SYS_PMSCR_EL1_PA_SHIFT         4
-#define SYS_PMSCR_EL1_TS_SHIFT         5
-#define SYS_PMSCR_EL1_PCT_SHIFT                6
-
-#define SYS_PMSCR_EL2                  sys_reg(3, 4, 9, 9, 0)
-#define SYS_PMSCR_EL2_E0HSPE_SHIFT     0
-#define SYS_PMSCR_EL2_E2SPE_SHIFT      1
-#define SYS_PMSCR_EL2_CX_SHIFT         3
-#define SYS_PMSCR_EL2_PA_SHIFT         4
-#define SYS_PMSCR_EL2_TS_SHIFT         5
-#define SYS_PMSCR_EL2_PCT_SHIFT                6
-
-#define SYS_PMSICR_EL1                 sys_reg(3, 0, 9, 9, 2)
-
-#define SYS_PMSIRR_EL1                 sys_reg(3, 0, 9, 9, 3)
-#define SYS_PMSIRR_EL1_RND_SHIFT       0
-#define SYS_PMSIRR_EL1_INTERVAL_SHIFT  8
-#define SYS_PMSIRR_EL1_INTERVAL_MASK   0xffffffUL
-
-/* Filtering controls */
-#define SYS_PMSNEVFR_EL1               sys_reg(3, 0, 9, 9, 1)
-
-#define SYS_PMSFCR_EL1                 sys_reg(3, 0, 9, 9, 4)
-#define SYS_PMSFCR_EL1_FE_SHIFT                0
-#define SYS_PMSFCR_EL1_FT_SHIFT                1
-#define SYS_PMSFCR_EL1_FL_SHIFT                2
-#define SYS_PMSFCR_EL1_B_SHIFT         16
-#define SYS_PMSFCR_EL1_LD_SHIFT                17
-#define SYS_PMSFCR_EL1_ST_SHIFT                18
-
-#define SYS_PMSEVFR_EL1                        sys_reg(3, 0, 9, 9, 5)
-#define SYS_PMSEVFR_EL1_RES0_8_2       \
+#define PMSEVFR_EL1_RES0_IMP   \
        (GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\
         BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0))
-#define SYS_PMSEVFR_EL1_RES0_8_3       \
-       (SYS_PMSEVFR_EL1_RES0_8_2 & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11)))
-
-#define SYS_PMSLATFR_EL1               sys_reg(3, 0, 9, 9, 6)
-#define SYS_PMSLATFR_EL1_MINLAT_SHIFT  0
-
-/* Buffer controls */
-#define SYS_PMBLIMITR_EL1              sys_reg(3, 0, 9, 10, 0)
-#define SYS_PMBLIMITR_EL1_E_SHIFT      0
-#define SYS_PMBLIMITR_EL1_FM_SHIFT     1
-#define SYS_PMBLIMITR_EL1_FM_MASK      0x3UL
-#define SYS_PMBLIMITR_EL1_FM_STOP_IRQ  (0 << SYS_PMBLIMITR_EL1_FM_SHIFT)
-
-#define SYS_PMBPTR_EL1                 sys_reg(3, 0, 9, 10, 1)
+#define PMSEVFR_EL1_RES0_V1P1  \
+       (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11)))
+#define PMSEVFR_EL1_RES0_V1P2  \
+       (PMSEVFR_EL1_RES0_V1P1 & ~BIT_ULL(6))
 
 /* Buffer error reporting */
-#define SYS_PMBSR_EL1                  sys_reg(3, 0, 9, 10, 3)
-#define SYS_PMBSR_EL1_COLL_SHIFT       16
-#define SYS_PMBSR_EL1_S_SHIFT          17
-#define SYS_PMBSR_EL1_EA_SHIFT         18
-#define SYS_PMBSR_EL1_DL_SHIFT         19
-#define SYS_PMBSR_EL1_EC_SHIFT         26
-#define SYS_PMBSR_EL1_EC_MASK          0x3fUL
-
-#define SYS_PMBSR_EL1_EC_BUF           (0x0UL << SYS_PMBSR_EL1_EC_SHIFT)
-#define SYS_PMBSR_EL1_EC_FAULT_S1      (0x24UL << SYS_PMBSR_EL1_EC_SHIFT)
-#define SYS_PMBSR_EL1_EC_FAULT_S2      (0x25UL << SYS_PMBSR_EL1_EC_SHIFT)
-
-#define SYS_PMBSR_EL1_FAULT_FSC_SHIFT  0
-#define SYS_PMBSR_EL1_FAULT_FSC_MASK   0x3fUL
+#define PMBSR_EL1_FAULT_FSC_SHIFT      PMBSR_EL1_MSS_SHIFT
+#define PMBSR_EL1_FAULT_FSC_MASK       PMBSR_EL1_MSS_MASK
 
-#define SYS_PMBSR_EL1_BUF_BSC_SHIFT    0
-#define SYS_PMBSR_EL1_BUF_BSC_MASK     0x3fUL
+#define PMBSR_EL1_BUF_BSC_SHIFT                PMBSR_EL1_MSS_SHIFT
+#define PMBSR_EL1_BUF_BSC_MASK         PMBSR_EL1_MSS_MASK
 
-#define SYS_PMBSR_EL1_BUF_BSC_FULL     (0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT)
+#define PMBSR_EL1_BUF_BSC_FULL         0x1UL
 
 /*** End of Statistical Profiling Extension ***/
 
@@ -575,6 +496,7 @@
 #define SCTLR_ELx_DSSBS        (BIT(44))
 #define SCTLR_ELx_ATA  (BIT(43))
 
+#define SCTLR_ELx_EE_SHIFT     25
 #define SCTLR_ELx_ENIA_SHIFT   31
 
 #define SCTLR_ELx_ITFSB         (BIT(37))
@@ -583,7 +505,7 @@
 #define SCTLR_ELx_LSMAOE (BIT(29))
 #define SCTLR_ELx_nTLSMD (BIT(28))
 #define SCTLR_ELx_ENDA  (BIT(27))
-#define SCTLR_ELx_EE     (BIT(25))
+#define SCTLR_ELx_EE     (BIT(SCTLR_ELx_EE_SHIFT))
 #define SCTLR_ELx_EIS   (BIT(22))
 #define SCTLR_ELx_IESB  (BIT(21))
 #define SCTLR_ELx_TSCXT         (BIT(20))
@@ -809,8 +731,8 @@
 
 #define ARM64_FEATURE_FIELD_BITS       4
 
-/* Create a mask for the feature bits of the specified feature. */
-#define ARM64_FEATURE_MASK(x)  (GENMASK_ULL(x##_SHIFT + ARM64_FEATURE_FIELD_BITS - 1, x##_SHIFT))
+/* Defined for compatibility only, do not add new users. */
+#define ARM64_FEATURE_MASK(x)  (x##_MASK)
 
 #ifdef __ASSEMBLY__